LTC2315HTS8-12 vs LTC2313HTS8-14 比較
詳細な並列比較: LTC2315HTS8-12 メーカー: Analog Devices および LTC2313HTS8-14 メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Analog Devices
LTC2315HTS8-12 - 12-Bit 5Msps SAR ADC in TSOT-23 | Analog Devices
LTC2315HTS8-12 ✓ 生産中Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ 生産中仕様比較
| パラメータ | LTC2315HTS8-12 | LTC2313HTS8-14 |
|---|---|---|
| ブランド | Analog Devices | Analog Devices |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $4.32 | $4.10 |
| Manufacturer | Analog Devices | — |
| Part Family | LTC2315-12 | — |
| 分解能 | 12 bit | 14 bits |
| サンプリングレート | 5 Msps | — |
| Architecture | SAR (Successive Approximation Register) | SAR (Successive Approximation Register) |
| Number of Channels | 1 input | — |
| Input Type | Single-ended / Pseudo-differential (true-sampling front end) | Pseudo-differential (IN+, IN-) |
| Analog Supply Voltage | 2.7 V to 5.25 V | — |
| Supply Current (Active, typ) | 6.4 mA | — |
| Reference | Internal bandgap with integrated buffer, 20 ppm/°C max drift | — |
| SINAD | 72.6 dB | — |
| THD | -84 dB | — |
| Digital Interface | SPI-compatible serial, 1.8 V / 2.5 V / 3 V / 5 V logic | — |
| Power-Down Modes | Nap and Sleep modes | — |
| パッケージ | TSOT-23-8 (8-pin) | TSOT-23-8 (HTS8) |
| 実装タイプ | Surface Mount | Surface Mount |
| Operating Temperature (H-grade) | -40 °C to +125 °C | — |
| RoHS ステータス | Compliant (per Analog Devices product page) | Compliant |
| Sample Rate | — | 2.5 Msps |
| Number of Input Channels | — | 1 (single-ended/differential) |
| 電源電圧 | — | 3 V to 5 V (single supply, 5 V typical) |
| 電源電流 | — | 5 mA at 2.5 Msps |
| Internal Reference | — | 2.5 V nominal, 20 ppm/°C max drift |
| Serial Interface | — | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| 動作温度範囲 | — | -40 °C to +125 °C (H-grade) |
| MSLレベル | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |