M1AFS250-PQ208 vs M1AFS250-1PQ208I 比較
詳細な並列比較: M1AFS250-PQ208 メーカー: Microsemi および M1AFS250-1PQ208I メーカー: Microchip Technology。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Microchip Technology
M1AFS250-1PQ208I - Fusion FPGA 250K Gates 208-QFP | Microchip
M1AFS250-1PQ208I ✓ 生産中仕様比較
| パラメータ | M1AFS250-PQ208 | M1AFS250-1PQ208I |
|---|---|---|
| ブランド | Microsemi | Microchip Technology |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $28.60 | $47.80 |
| Logic Gates | 250000 gates | — |
| Fabric Cells / VersaTiles | 6144 cells | — |
| Number of I/O | 93 | — |
| User Flash Memory | 36864 bits | — |
| Core Supply Voltage | 1.5 V | — |
| Process Technology | 130 nm flash CMOS | — |
| Configuration Memory | Flash-based, on-chip (nonvolatile) | Flash (non-volatile, single-chip) |
| Security | 128-bit flash lock, AES decryption | — |
| パッケージ | 208-Pin PQFP / BFQFP | 208-pin PQFP (PQ208 / BFQFP) |
| Terminal Pitch | 0.5 mm | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Analog Blocks | Configurable analog (ADC inputs, monitoring) per Fusion family | — |
| Clock Management | On-chip PLL / clock conditioning circuitry | Clock Conditioning Circuits (CCC) |
| Power-Up Behavior | Functional immediately at power-up (no external boot device) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Compliant (non-Pb PQ208 version is M1AFS250-1PQ208I; PQG208 is Pb-free variant naming) |
| Max Frequency Reference | 1098.9 MHz (family listing per Kynix) | — |
| Logic Cells (Tiles) | — | 6144 |
| Equivalent Gates | — | 250000 |
| User I/O | — | 93 |
| RAM Bits | — | 36864 |
| Family | — | Fusion (M1) Mixed-Signal FPGA |
| Core Voltage | — | 1.5 V |
| Technology | — | 130 nm CMOS Flash |
| Speed Grade | — | -1 |
| Analog Peripherals | — | Configurable analog blocks (voltage, temperature, current monitoring) |
| MSLレベル | — | [DATA_NEEDED: MSL Level] |
| Radiation Characteristic | — | Flash-based, immune to configuration upset vs SRAM FPGAs |