MC145572PBR2 vs MX574ALEWI+TCDR 比較
詳細な並列比較: MC145572PBR2 メーカー: NXP Semiconductors および MX574ALEWI+TCDR メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP
MC145572PBR2 ObsoleteAnalog Devices
MX574ALEWI+TCDR - 12-Bit 25µs SAR ADC, 28-SOIC | Maxim Integrated
MX574ALEWI+TCDR ✓ 生産中仕様比較
| パラメータ | MC145572PBR2 | MX574ALEWI+TCDR |
|---|---|---|
| ブランド | NXP Semiconductors | Analog Devices |
| カテゴリ | Interface ICs | ADC/DAC |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.20 | $17.10 |
| Part Type | ISDN U-Interface Transceiver | — |
| Manufacturer | NXP Semiconductors (formerly Freescale / Motorola) | Analog Devices Inc. (formerly Maxim Integrated) |
| 電源電圧 | 5 V (typical) | — |
| データレート | 160 kbps (2B1Q full-duplex over single twisted pair) | — |
| Line Code | 2B1Q (ANSI T1.601-1992) | — |
| Interface Standard | ANSI T1.601-1992 / ETSI ETR 080 | — |
| Operating Modes | NT (Network Termination) and LT (Line Termination), strap-selectable | — |
| HDLC Controller | On-chip, up to 4x 16-bit or 2x 32-bit identifiers | — |
| Echo Canceller | Integrated adaptive | — |
| Scrambler/Descrambler | On-chip | — |
| Host Interface | Parallel microprocessor-compatible | — |
| パッケージ | 44-LQFP (10x10 mm) | 28-pin SOIC wide-body (SOIC-28W) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial, 'L' grade) |
| RoHS ステータス | RoHS non-compliant (SnPb finish, per legacy Freescale data) | Compliant |
| Lead-Free Status | Contains lead (legacy PBR2 tape-and-reel part marking) | — |
| Series | MC145572 | — |
| Part Status | Obsolete / Last-time-buy stock only | — |
| MPN | — | MX574ALEWI+TCDR |
| Converter Type | — | SAR (Successive Approximation Register) ADC |
| 分解能 | — | 12 bit |
| Number of Inputs | — | 1 |
| Input Type | — | Single-Ended (unipolar or bipolar ranges via pin strapping) |
| Maximum Conversion Time | — | 25 µs |
| Sample Rate (max) | — | 40 kSPS (typ) |
| Analog Input Ranges | — | 0 to +5 V, 0 to +10 V, ±5 V, ±10 V (software/strap-selectable) |
| Internal Reference | — | +10 V buried Zener, ±0.25 % initial accuracy (typ) |
| Data Interface | — | 12-bit parallel, 8-bit parallel, or serial |
| 出力タイプ | — | Three-state (high-Z) CMOS-compatible |
| Integral Nonlinearity (A grade) | — | ±1 LSB (max) |
| Supply Voltages | — | V+ = +12 V or +15 V, V- = -12 V or -15 V, VCC (digital) = +5 V |
| Power Consumption | — | 150 mW (typ, ±15 V supply) |
| AEC-Q100 | — | Not qualified (commercial grade) |