MC145572PBR2 vs MX574ALEWI+TCDR Comparaison

Comparaison détaillée côte à côte de MC145572PBR2 par NXP Semiconductors et MX574ALEWI+TCDR par Analog Devices. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.

NXP Semiconductors
MC145572PBR2 MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP

MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP

MC145572PBR2 Obsolete

Comparaison des spécifications

Paramètre MC145572PBR2 MX574ALEWI+TCDR
Marque NXP Semiconductors Analog Devices
Catégorie Interface ICs ADC/DAC
Statut du cycle de vie Obsolete Actif
Statut du stock In Stock In Stock
Prix unitaire (USD) $5,20 $17,10
Part Type ISDN U-Interface Transceiver —
Manufacturer NXP Semiconductors (formerly Freescale / Motorola) Analog Devices Inc. (formerly Maxim Integrated)
Tension d'alimentation 5 V (typical) —
Débit de données 160 kbps (2B1Q full-duplex over single twisted pair) —
Line Code 2B1Q (ANSI T1.601-1992) —
Interface Standard ANSI T1.601-1992 / ETSI ETR 080 —
Operating Modes NT (Network Termination) and LT (Line Termination), strap-selectable —
HDLC Controller On-chip, up to 4x 16-bit or 2x 32-bit identifiers —
Echo Canceller Integrated adaptive —
Scrambler/Descrambler On-chip —
Host Interface Parallel microprocessor-compatible —
Boîtier 44-LQFP (10x10 mm) 28-pin SOIC wide-body (SOIC-28W)
Type de montage Surface Mount Surface Mount
Température de fonctionnement [DATA_NEEDED: operating temperature range] 0 °C to +70 °C (commercial, 'L' grade)
Statut RoHS RoHS non-compliant (SnPb finish, per legacy Freescale data) Compliant
Lead-Free Status Contains lead (legacy PBR2 tape-and-reel part marking) —
Series MC145572 —
Part Status Obsolete / Last-time-buy stock only —
MPN — MX574ALEWI+TCDR
Converter Type — SAR (Successive Approximation Register) ADC
Résolution — 12 bit
Number of Inputs — 1
Input Type — Single-Ended (unipolar or bipolar ranges via pin strapping)
Maximum Conversion Time — 25 µs
Sample Rate (max) — 40 kSPS (typ)
Analog Input Ranges — 0 to +5 V, 0 to +10 V, ±5 V, ±10 V (software/strap-selectable)
Internal Reference — +10 V buried Zener, ±0.25 % initial accuracy (typ)
Data Interface — 12-bit parallel, 8-bit parallel, or serial
Type de sortie — Three-state (high-Z) CMOS-compatible
Integral Nonlinearity (A grade) — ±1 LSB (max)
Supply Voltages — V+ = +12 V or +15 V, V- = -12 V or -15 V, VCC (digital) = +5 V
Power Consumption — 150 mW (typ, ±15 V supply)
AEC-Q100 — Not qualified (commercial grade)

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