P2010NSE2HFC vs P2020NSE2HFC 比較
詳細な並列比較: P2010NSE2HFC メーカー: NXP Semiconductors および P2020NSE2HFC メーカー: NXP Semiconductors。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
P2010NSE2HFC - QorIQ P2 800MHz Power Arch SoC | NXP | Networking
P2010NSE2HFC ✗ 生産終了NXP Semiconductors
P2020NSE2HFC - QorIQ P2 Dual-Core 1.2GHz SoC | NXP Semiconductors
P2020NSE2HFC ✓ 生産中仕様比較
| パラメータ | P2010NSE2HFC | P2020NSE2HFC |
|---|---|---|
| ブランド | NXP Semiconductors | NXP Semiconductors |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | 製造終了 | 有効 |
| Manufacturer | NXP Semiconductors | — |
| Product Family | QorIQ P2 | — |
| Architecture | Power Architecture e500v2 | — |
| Core Count | 1 | — |
| Bit Width | 32-bit | — |
| CPU Frequency | 800 MHz | — |
| Memory Controller | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC |
| Gigabit Ethernet | 3 (10/100/1000 Mbps) | — |
| PCIe Controllers | 3 (PCIe 1.0) | — |
| Serial RapidIO (SRIO) | 2 lanes | — |
| USB | USB 2.0 | USB 2.0 Host/Device |
| Security Accelerator | SEC (DES/3DES/AES/RSA/ECC) | — |
| Process Technology | 45 nm | — |
| パッケージ | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II 31x31 mm with exposed pad |
| 動作温度 | 0 to 125 C | — |
| Temperature Grade | Commercial (HFC suffix) | — |
| 電源電圧 | [DATA_NEEDED: core/IO supply voltage] | [DATA_NEEDED: core voltage] |
| Power Dissipation (typ) | [DATA_NEEDED: typical power at 800 MHz] | — |
| L1 I-Cache / D-Cache | 32 KB / 32 KB | — |
| 実装タイプ | Surface Mount (BGA) | — |
| Lead Free | Yes | — |
| RoHS ステータス | Compliant | Compliant |
| Packaging | Tray | — |
| Revision | Rev 2.1 | — |
| Family | — | QorIQ P2 |
| Core Architecture | — | PowerPC e500v2 |
| Number of Cores | — | 2 |
| データバス幅 | — | 32-bit |
| Maximum Core Frequency | — | 1.2 GHz |
| 動作温度範囲 | — | 0 °C to +125 °C |
| Co-Processor / Security Engine | — | SEC 3.3 (IPsec/SSL/3GPP) |
| Ethernet Interfaces | — | 10/100/1000 Mbps (RGMII), dual GbE |
| PCI Express | — | PCIe Gen 1.1 x1/x2/x4 controllers |
| Serial RapidIO | — | 2x SRIO ports |
| UART | — | 4x UART |
| I2C / SPI / SDHC | — | Yes (2x I2C, SPI, SDHC) |
| NAND Flash Controller | — | Yes |
| L1 Cache (per core) | — | 32 KB I-cache + 32 KB D-cache |
| L2 Cache (shared) | — | 512 KB |