XA7A12T-2CSG325I vs XC7A12T-2CSG325I 比較
詳細な並列比較: XA7A12T-2CSG325I メーカー: AMD および XC7A12T-2CSG325I メーカー: AMD。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | XA7A12T-2CSG325I | XC7A12T-2CSG325I |
|---|---|---|
| ブランド | AMD | AMD |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| Family | Artix-7 XA (Automotive) | — |
| Logic Cells | 12800 | 12,800 cells |
| Configurable Logic Blocks (Slices) | 2000 | — |
| Distributed RAM | 125 Kb | — |
| DSP48E1 Slices | 40 | — |
| Block RAM Blocks | 20 x 36 Kb | — |
| Total Block RAM | 737280 bits | — |
| User I/O | 150 | 150 I/Os |
| パッケージ | 324-LFBGA, CSPBGA (CSG325) | 324-LFBGA CSBGA |
| Speed Grade | -2 | — |
| Core Supply Voltage (VCCINT) | 1.0 V | — |
| I/O Voltage Range (HR Banks) | 1.2 V to 3.3 V | — |
| Operating Temperature (Tj) | -40 C to +100 C (Industrial) | — |
| 湿気感度レベル（MSL） | 3 | — |
| Peak Reflow Temperature | 260 C | — |
| Maximum Time at Peak Reflow | 30 s | — |
| Terminal Finish | Tin/Silver/Copper (JESD-609 e1) | — |
| Automotive Qualification | AEC-Q100 (XA flow) | — |
| Configuration Modes | Master SPI, Master BPI, Slave SelectMAP, Slave Serial, JTAG | — |
| Device Type | — | Artix-7 FPGA |
| Configuration Memory | — | 737,280 bits |
| Performance Grade | — | -2 |
| Process Technology | — | 28 nm HKMG HPL |
| Package Type | — | CSPBGA |
| 実装タイプ | — | Surface Mount |
| Programmable Logic Type | — | FPGA |
| Product Family | — | Artix-7 |
| Number of Logic Cells | — | 12,800 cells |
| Number of User I/Os | — | 150 I/Os |
| Silicon Technology | — | 28 nm HKMG HPL process |
| RoHS ステータス | — | Compliant |
| 動作温度範囲 | — | [DATA_NEEDED: operating temperature range] |
| Supply Voltage Range | — | [DATA_NEEDED: core and I/O supply voltage ranges] |
| Block RAM Capacity | — | [DATA_NEEDED: block RAM capacity] |
| DSP Slice Count | — | [DATA_NEEDED: DSP slice count] |
| 最大クロック周波数 | — | [DATA_NEEDED: maximum clock frequency] |
| I/O Standard Support | — | [DATA_NEEDED: supported I/O standards] |