10AS057H3F34I2LG - Arria 10 SX SoC FPGA, 570K LE, Dual ARM Cortex-A9 | Intel
部品番号: 10AS057H3F34I2LG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3703.81 | $3,703.81 |
| 10 | $3500 | $35,000.00 |
| 100 | $3300 | $330,000.00 |
| 500 | $3150 | $1,575,000.00 |
| 1,000 | $2950 | $2,950,000.00 |
10AS057H3F34I2LG 概要
This product type, a SoC FPGA, combines a hardened application processor subsystem with general-purpose FPGA fabric on a single die, occupying the design space between traditional microcontrollers (which lack programmable logic) and conventional FPGAs (which lack an integrated CPU). The Arria 10 SX family is Intel's mid-range SoC FPGA, positioned below the high-end Stratix 10 SX and above the entry-level Cyclone V SoC, serving industrial, wireless, broadcast, and defense applications that need both deterministic hardware acceleration and a Linux-capable application processor.
Key features include 570K logic elements, 1.5 GHz maximum Cortex-A9 core frequency, 16.7 Gbps transceivers for high-speed serial I/O, and integrated DDR3/DDR4 hard memory controllers. The 'I2' speed/temperature grade designation indicates an industrial temperature range (-40C to +100C junction) with a mid-speed bin, while the 'F34' suffix identifies the FCBGA-1152 package option.
The Arria 10 SX architecture pairs a 20nm process-node FPGA fabric with a dedicated ARM-based HPS connected via a high-bandwidth system interconnect. This allows software-driven control planes to coexist with low-latency hardware-accelerated dataplanes, which is essential for motor control, protocol bridging, and DSP front-end processing in radar or 5G fronthaul.
Typical applications include industrial motor drives, 5G remote-radio-head baseband, broadcast video processing, military/aerospace signal intelligence, medical imaging pre-processing, and ADAS sensor fusion platforms. The dual-core Cortex-A9 runs Linux/RTOS for housekeeping while the FPGA fabric handles data-plane DSP.
When designing with this device, allocate sufficient PCB area for the 35x35 mm FCBGA and use a minimum 8-layer stackup with via-in-pad capability for clean power delivery. The HPS and FPGA fabric each require independent power rails; sequencing must follow the Intel Enpirion reference design.
This page synthesizes distributor pricing, drop-in alternative MPNs from the same Arria 10 SX family, and practical design considerations not consolidated in the manufacturer datasheet.
ドロップイン代替品: 10AS057H3F34I2LG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AS057H3F34I2LG （同一形状・フットプリント） — 相違点: Package, Logic Elements, Speed Grade, Transceivers, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
10AS057H3F34I3LG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10AS057H3F34E2LG
✅ ドロップイン✓ 在庫あり
$2485 / 個
データシートを見る →10AS057H2F34I2LG
✅ ドロップイン✓ 在庫あり
$3675 / 個
データシートを見る →10AS057H2F34I2SG
✅ ドロップイン✓ 在庫あり
$7100 / 個
データシートを見る →10AS066H3F34I2LG
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →10AS048H3F34I2LG
✅ ドロップイン✓ 在庫あり
$2960 / 個
データシートを見る →10AS048H3F34I2SG
✅ ドロップイン✓ 在庫あり
$3450 / 個
データシートを見る →10AS057H3F34I2LG 最大定格＆電気的特性
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570 K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Core Frequency | 1.5 GHz |
| パッケージ | 1152-ball FCBGA (F34, 35x35 mm) |
| 実装タイプ | Surface Mount |
| Process Node | 20 nm |
| Operating Temperature (Industrial) | -40 C to +100 C (junction) |
| Speed Grade | I2 (mid-speed, industrial) |
| User I/O | 492 (per Heisener listing) |
| Transceivers | Up to 16.7 Gbps (per Arria 10 family) |
| Hard Memory Controllers | DDR3/DDR4 with ECC |
| RoHS ステータス | Compliant |
10AS057H3F34I2LG ピン構成
| ピン 1 | F34-B1 — Bank 1A user I/O / HPS ball (see Arria 10 SX pinout file) |
| ピン 2 | F34-B2 — Bank 1A user I/O / HPS ball |
| ピン 3 | VCC — Core/auxiliary supply ball (per bank assignment) |
主な用途
10AS057H3F34I2LG の用途: 7 件s: Industrial Motor Drive Control, 5G Remote Radio Head (RRH) Baseband, Broadcast Video Processing, Military / Aerospace Signal Intelligence, Medical Imaging Pre-Processing, ADAS Sensor Fusion Platform, Test & Measurement Instrumentation.
Industrial Motor Drive Control
The 10AS057H3F34I2LG is well-suited to industrial motor drives because the dual-core ARM Cortex-A9 HPS at 1.5 GHz can run field-oriented control loops and Modbus/EtherCAT communication stacks while the 570K-LE FPGA fabric handles high-rate PWM generation, encoder feedback sampling, and hardware safety logic. The 16.7 Gbps transceivers simplify connection to high-speed isolated gate drivers, and the FCBGA-1152 package's industrial I2 grade (-40C to +100C junction) supports harsh factory-floor environments.
おすすめ
5G Remote Radio Head (RRH) Baseband
In 5G RRH applications the 10AS057H3F34I2LG delivers the FPGA fabric bandwidth needed for CPRI/eCPRI fronthaul up to 16.7 Gbps per transceiver lane, while the ARM Cortex-A9 HPS runs the O-RAN real-time scheduler and PHY management layer. The integrated DDR4 hard memory controller with ECC provides reliable buffering for IQ sample streams, and the 1152-FCBGA thermal envelope is sufficient for sealed outdoor radio unit enclosures with forced-air cooling.
おすすめ
Broadcast Video Processing
The 10AS057H3F34I2LG serves broadcast video processing roles such as 12G-SDI routing, HDR/WCG conversion, and UHD frame synchronization. The 570K LE fabric handles multi-channel video scaling and deinterlacing at 4K60, while the HPS runs control plane software for IP-based control (NMOS IS-04/IS-05). The 16.7 Gbps transceivers enable SMPTE ST 2110 over 25G Ethernet, making the device a practical platform for IP broadcast studio cores.
おすすめ
Military / Aerospace Signal Intelligence
Defense signal-intelligence systems leverage the 10AS057H3F34I2LG's combination of wideband transceiver capability and dual-core HPS for processing radar warning, ELINT, and COMINT streams. The industrial temperature range allows deployment in ruggedized enclosures, and the HPS runs crypto libraries while the FPGA accelerates FFT, channelization, and deinterleaving. Conformal-coated board variants built around this part are common in airborne and naval ESM systems.
おすすめ
Medical Imaging Pre-Processing
In ultrasound and CT imaging front-ends the 10AS057H3F34I2LG pre-processes raw transducer data at wire-rate: beamforming, matched filtering, and harmonic separation are offloaded to the 570K-LE FPGA fabric, while the dual-core ARM Cortex-A9 handles beam-line API, image reconstruction scheduling, and DICOM metadata tagging. The FCBGA-1152 industrial-grade thermal profile supports integration inside cart-based ultrasound systems with passive heatsinks.
おすすめ
ADAS Sensor Fusion Platform
Automotive ADAS domain controllers use the 10AS057H3F34I2LG to fuse data from multiple camera, radar, and lidar sensors. The FPGA fabric delivers deterministic low-latency sensor pre-processing (object detection, free-space estimation) while the ARM Cortex-A9 HPS runs AUTOSAR-compliant vehicle middleware, sensor arbitration, and Ethernet AVB/TSN stack. The 16.7 Gbps transceivers accommodate automotive Ethernet and FPD-Link III camera aggregation links.
おすすめ
Test & Measurement Instrumentation
Modular T&M instruments (digitizers, protocol analyzers, oscilloscope front-ends) leverage the 10AS057H3F34I2LG's high-speed transceivers and parallel DSP fabric for real-time signal acquisition and triggering. The HPS runs the user-interface web server, SCPI command parser, and LXI stack, exposing the FPGA-accelerated measurement engine over standard interfaces. Designers benefit from Quartus Prime's DSP Builder for MATLAB/Simulink integration, accelerating waveform algorithm development.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AS057H3F34I2LG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AS057H3F34I3LG | 10AS057H3F34E2LG | 10AS057H2F34I2LG | 10AS066H3F34I2LG | 10AS048H3F34I2LG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FCBGA (F34, 35x35 mm) | 1152-FCBGA (F34, 35x35 mm) - same | 1152-FCBGA (F34, 35x35 mm) - same | 1152-FCBGA (F34, 35x35 mm) - same | 1152-FCBGA (F34, 35x35 mm) - same | 1152-FCBGA (F34, 35x35 mm) - same |
| Logic Elements | 570 K | 570 K | 570 K | 570 K | 660 K | 480 K |
| Speed/Temperature Grade | I2 (industrial mid-speed) | I3 (industrial fastest) | E2 (commercial) | I2 (industrial) | I2 (industrial) | I2 (industrial) |
| HPS Core | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz |
| Operating Junction Temperature | -40 C to +100 C (industrial) | -40 C to +100 C | 0 C to +85 C (commercial) | -40 C to +100 C | -40 C to +100 C | -40 C to +100 C |
| Transceiver Data Rate | Up to 16.7 Gbps | Up to 16.7 Gbps | Up to 16.7 Gbps | Up to 16.7 Gbps | Up to 16.7 Gbps | Up to 16.7 Gbps |
主な差別化要因
- Highest 570K LE option within the I2 industrial grade for F34 package （vs 10AS048H3F34I2LG (480K LE))
- Better speed/temperature balance than H2 variant （vs 10AS057H2F34I2LG (H2 variant))
- Industrial temperature vs commercial-only alternative （vs 10AS057H3F34E2LG (E2 commercial grade))
設計ノート
The 1152-ball FCBGA at 35x35 mm requires via-in-pad (VIP) processing and at minimum an 8-layer PCB stackup to maintain signal integrity for the 16.7 Gbps transceivers. Use 1 oz copper on outer layers with microvia stacks from BGA breakouts to inner signal layers. Follow Intel's Arria 10 SX board design guidelines for trace length matching on DDR4 channels and reference stackup impedance targets (100 ohm differential for transceivers).
Arria 10 SX SoC FPGAs require multiple independent rails: 0.9V core (VCC, VCCP), 1.8V auxiliary (VCCPT), 1.2V/1.5V transceiver supplies (VCCR/VCCT/VCCM), and 3.3V/2.5V I/O (VCCIO). Each bank may have a different VCCIO. Power sequencing must follow Intel's Power-Up and Power-Down Sequence specification; missing this risks latch-up. Estimate: at full HPS + fabric utilization on the 570K device, total board power is typically 15-25 W depending on toggle rate.
Estimated: with a typical 20 W dissipation and a 35x35 mm FCBGA on a JEDEC 4-layer test board with natural convection, junction-to-ambient theta_JA is roughly 8-10 C/W. This yields a junction rise of ~160-200 C above ambient at full load - clearly above the 100 C industrial limit. Attach a heat spreader and integrate a heat sink with thermal interface material, or use forced-air cooling, especially inside sealed enclosures.
A common pitfall is treating the HPS as a stand-alone CPU and ignoring the FPGA-to-HPS bridge (FPGA-to-SDRAM, FPGA-to-IO). Boot the HPS from QSPI flash (e.g., N25Q256A13EF8A0F) and ensure the FPGA core image is staged to a location the HPS can hand off via the System Manager firmware. Also enable ECC on HPS DDR4 - uncorrectable single-bit errors will otherwise silently corrupt Linux user-space data.
コンプライアンス情報
RoHS compliant per Intel/Altera material declaration. Not AEC-Q100 qualified - consult Intel automotive-grade Cyclone V or MAX 10 families for AEC-Q100 requirements. Halogen-free status not stated in the provided data.
