10AS057K4F35E3SG - Arria 10 SX SoC FPGA, 570K LE, 1.5GHz | Altera
部品番号: 10AS057K4F35E3SG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $2510.31 | $2,510.31 |
| 10 | $2280 | $22,800.00 |
| 100 | $2050 | $205,000.00 |
| 500 | $1850 | $925,000.00 |
| 1,000 | $1700 | $1,700,000.00 |
10AS057K4F35E3SG 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device built from an array of configurable logic blocks (CLBs), dedicated DSP blocks, on-chip memory, and high-speed transceiver slices connected by a programmable routing fabric. A System-on-Chip FPGA adds a hard processor subsystem (HPS) - in Arria 10 SX, a dual-core ARM Cortex-A9 with caches, NEON media engine, and CoreSight debug - so designers can partition control-plane code onto a real CPU while accelerating data-plane work in fabric. The Arria 10 family is built on TSMC's 20 nm process and targets mid-range DSP, transceiver bandwidth, and ARM-based embedded workloads.
Key features of the 10AS057K4F35E3SG variant include the 570K logic-element count (mid-density Arria 10 SX), up to 1.5 GHz Cortex-A9 dual-core HPS, integrated CoreSight debug, and the -3 speed grade indicating a faster fabric timing bin. The 1152-ball FCBGA package exposes the high I/O count and dedicated transceiver/clock pin assignments required by mid-range Arria 10 designs; finer details such as exact transceiver count and DSP block count require the Arria 10 family datasheet and device-specific addendum.
The 10AS057K4F35E3SG blends a deterministic, Linux-capable Cortex-A9 HPS with hardened memory controllers and high-throughput serial transceivers, enabling single-chip designs that previously required an external processor plus a separate FPGA. Designers use it for protocol bridging, motor/control loops, and data-pipeline preprocessing where a deterministic real-time fabric must interoperate with a managed OS.
Typical applications include wireless baseband preprocessing, industrial motor control with Linux supervisory layer, medical imaging front-ends, broadcast video processing, and military/aerospace signal intelligence prototypes. The dual-core ARM HPS allows a real-time OS (RTOS) and Linux to share the chip for partitioned workloads.
When designing with this device, use Quartus Prime SoC Edition (Standard or Pro) for both FPGA bitstream and HPS first-stage bootloader (FSBL) generation, and use the Arria 10 SoC development kit (available separately) as a reference for power-rail sequencing, DDR3/4 pin assignment, and transceiver reference clock routing. Pinout, transceiver channel mapping, and HPS peripheral pin multiplexing are documented in the Arria 10 family datasheet and device errata.
This page consolidates distributor pricing, parametric drop-in alternatives, and design considerations not surfaced in the manufacturer ordering part-number page, giving engineers a single reference for sourcing and substitution decisions.
ドロップイン代替品: 10AS057K4F35E3SG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AS057K4F35E3SG （同一形状・フットプリント） — 相違点: Mounting Type, Package, Speed Grade, Logic Elements, Hard Processor System.
クイック比較ツール — 並列比較する代替部品を選択:
10AS057K4F35E3LG
✅ ドロップイン✓ 在庫あり
$2990 / 個
データシートを見る →10AS057K4F35I3SG
✅ ドロップイン✓ 在庫あり
$2185 / 個
データシートを見る →10AS057K4F35I3LG
✅ ドロップイン✓ 在庫あり
$2998.88 / 個
データシートを見る →10AS057K3F35E2SG
✅ ドロップイン✓ 在庫あり
$3740 / 個
データシートを見る →10AS057K3F35E2LG
✅ ドロップイン✓ 在庫あり
$2950 / 個
データシートを見る →10AS057K2F35E2SG
✅ ドロップイン✓ 在庫あり
$2304.55 / 個
データシートを見る →10AS057H4F35E3SG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10AS057K4F35E3SG 最大定格＆電気的特性
| Family | Arria 10 SX |
| Series / Device | 10AS057 |
| Device Type | System-on-Chip FPGA (SoC FPGA) |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 570000 (570K) |
| Maximum HPS Core Frequency | 1.5 GHz |
| Speed Grade | -3 (fastest) |
| パッケージ | 1152-FBGA, FC (35x35 mm) |
| 実装タイプ | Surface Mount |
| Process Node | 20 nm (TSMC) |
| Operating Temperature Grade | E (Enhanced, industrial) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
| I/O Count (approx.) | 396 user I/O per supplier listing |
10AS057K4F35E3SG 1152-fbga, fc (35x35 mm) ピン配置ガイド
10AS057K4F35E3SG (1152-fbga, fc (35x35 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 10AS057K4F35E3SG.
詳細は データシート をご参照ください。
主な用途
10AS057K4F35E3SG の用途: 6 件s: Wireless Baseband Preprocessing, Industrial Motor Control with Linux Supervisor, Medical Imaging Front-End Processing, Broadcast Video Processing, Software Defined Radio (SDR) Prototyping, Aerospace and Defense Signal Intelligence.
Wireless Baseband Preprocessing
The 10AS057K4F35E3SG fits wireless baseband preprocessing because its 570K logic elements provide enough fabric for multi-antenna digital down-conversion, channelization, and crest-factor reduction ahead of the HPS. The 1.5 GHz dual-core Cortex-A9 runs LTE MAC scheduling or 5G NR low-PHY control, while the FPGA fabric handles deterministic radio pipelines at sample rates the ARM cannot sustain. The integrated CoreSight debug path simplifies tracing across fabric-accelerated and software-processed data, which is essential when correlating radio errors to specific DSP blocks. Designers can pair the SoC with a single transceiver mezzanine and host all PHY/MAC layers on one chip.
おすすめ
Industrial Motor Control with Linux Supervisor
For multi-axis FOC servo drives and EtherCAT master controllers, the 10AS057K4F35E3SG places real-time current/torque control loops in fabric while Linux on the dual-core Cortex-A9 handles the supervisory stack - HMI, telemetry, and remote firmware updates. The 570K logic-element fabric supports parallel control loops for 4-8 axes with encoder feedback and sigma-delta ADC interfaces, eliminating the latency jitter of a pure-software approach. Linux runs deterministically enough for EtherCAT distribution clock master, and the HPS Ethernet MAC pairs with an FPGA-side EtherCAT slave IP for cycle times below 250 us. This single-chip partition reduces BOM cost versus separate CPU + FPGA architectures.
おすすめ
Medical Imaging Front-End Processing
Ultrasound beamforming and optical coherence tomography front-ends demand deterministic low-latency DSP at line rates that the 10AS057K4F35E3SG handles efficiently. The FPGA fabric runs beamforming FIR filters, envelope detection, and image-formation pipelines at sample rates of 40-80 MHz, while the Cortex-A9 HPS assembles the resulting image frames and serves them to the user interface over Ethernet or USB. The 570K logic elements support 32-64 channel beamformers in a single chip, replacing previous multi-FPGA designs. Compliance with IEC 60601 patient-safety isolation and EMC requirements is achievable with proper PCB partitioning, leveraging the HPS for low-speed supervisory tasks.
おすすめ
Broadcast Video Processing
Broadcast video routers, multi-format converters, and IPTV head-ends benefit from the 10AS057K4F35E3SG's combination of high fabric throughput and Linux-based control plane. The 570K logic elements support SDI/HDMI cross-point switching, deinterlacing, and scaling at 4K/UHD rates using hardened video IP blocks. The dual-core ARM HPS runs SMP Linux with userspace drivers for SDI ancillary data extraction and IPTV packetization, offloading housekeeping from the fabric. The integrated CoreSight debug accelerates bring-up when chasing video timing issues across FPGA and software domains, a common pain point in broadcast design.
おすすめ
Software Defined Radio (SDR) Prototyping
The 10AS057K4F35E3SG is widely used in SDR prototyping because it pairs a 570K-LE FPGA with a Linux-capable dual-core ARM. Waveform-specific DSP (FFT, channel coding, polyphase filterbanks) runs in fabric for deterministic latency, while the Cortex-A9 hosts the GNU Radio or custom waveform stack for protocol-layer work. The HPS exposes standard Ethernet and USB peripherals for control and high-speed data streaming to a host workstation, simplifying lab setup. Designers benefit from the shared coherent memory between fabric and HPS, enabling zero-copy transfer of digitized I/Q buffers between accelerator and application.
おすすめ
Aerospace and Defense Signal Intelligence
Aerospace signal-intelligence and electronic-warfare prototypes use the 10AS057K4F35E3SG for its combination of mid-range fabric, ARM Cortex-A9 for ELINT/OSINT processing, and ruggedized industrial operating temperature. The 570K logic elements support wideband digital receivers, channelizers, and adaptive beamforming IP, while the HPS runs Java/OSGi-based mission applications. Designers can leverage the existing Arria 10 SX ecosystem (Quartus Prime SoC, U-Boot, Linux BSP) to shorten development cycles for defense programs. Pin-compatible variants in the 10AS057 family allow quick migration to higher temperature grades if mission profile demands.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AS057K4F35E3SG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AS057K4F35E3LG | 10AS057K4F35I3SG | 10AS057K3F35E2SG |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Family / Device | Arria 10 SX / 10AS057 | Arria 10 SX / 10AS057 | Arria 10 SX / 10AS057 | Arria 10 SX / 10AS057 |
| Logic Elements | 570K | 570K | 570K | 570K |
| HPS Core | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz |
| Speed Grade | -3 (fastest) | -3 | -3 | -2 (slower fabric) |
| Temperature Grade | Enhanced (E) | Enhanced (E) | Industrial (I) | Enhanced (E) |
| Lead-Free Finish | SG (SnPb/Gold) - non-Pb-free | LG (Pb-free) | SG (SnPb/Gold) | SG (SnPb/Gold) |
| Approx. Unit Price (1pc) | $2510.31 (as of 2026-09-05) | Similar; slight Pb-free premium | Similar to base | Lower (slower speed grade) |
主な差別化要因
- Hard ARM Cortex-A9 HPS integrated with 570K LE Arria 10 fabric （vs Xilinx Zynq-7000 XC7Z045)
- -3 speed grade delivers fastest fabric timing closure （vs 10AS057K3F35E2SG (-2 speed grade, same package))
- Lead-free LG variant available with identical die （vs 10AS057K4F35E3SG (SnPb/Gold finish, SG suffix))
設計ノート
Estimated: A 570K-logic-element Arria 10 SX at full fabric utilization typically dissipates 8-15 W depending on toggle rate and DSP utilization, plus 2-4 W for the dual-core Cortex-A9 HPS. The 1152-FBGA F35 package requires a multi-layer PCB with substantial ground plane and at least 2-3 thermal vias under the BGA array to keep junction temperature within the E-grade 100 C limit. Designers should budget a heatsink or cold plate for industrial deployment; reference thermal models are provided in the Arria 10 SoC development kit mechanical drawings. Always simulate worst-case with the Quartus Prime PowerPlay tool before final PCB layout.
The 1152-FBGA F35 package uses a 1.0 mm pitch ball array. PCB design must follow the Altera/Intel pin connection guidelines for the F35 package, including matched-length routing for DDR3/4 interfaces from the HPS and high-speed transceiver channels. Stackup should be at minimum 12 layers with dedicated ground and power planes to meet signal-integrity requirements for HPS memory and transceiver reference clocks. Use the Arria 10 SoC development kit schematic as a reference for HPS pin assignments and power-rail sequencing - the HPS requires coordinated power-up of the Cortex-A9 cores, peripherals, and DDR PHY for proper boot.
Estimated: A common pitfall is under-budgeting the HPS boot infrastructure - the Cortex-A9 needs a valid first-stage bootloader (FSBL), U-Boot SPL, and Linux device tree compiled for the F35 package pinout, all stored in QSPI flash alongside the FPGA bitstream. Designers often overlook that Quartus Prime SoC Edition requires a separate license from the base Quartus Prime Pro license, and that the HPS toolchain (ARM DS-5 or Intel SoC EDS) must match the Quartus version. Another pitfall is leaving transceiver reference-clock pins unassigned when migrating from a K-suffix to H-suffix variant - the H variant has more transceivers but different reference-clock pin assignments.
Estimated: For HPS Ethernet MAC, USB, and SD/MMC interfaces, keep trace lengths within the budgets specified in the Arria 10 device handbook and place series capacitors near the SoC pins per the reference schematic. The HPS DDR controller pins are not freely assignable; they map to fixed balls on the F35 package - consult the device pin-out file before PCB layout begins. Always include a USB-Blaster II header or JTAG test points for in-system programming and debug access, as field returns for SoC FPGAs without JTAG access are significantly more difficult to recover.
コンプライアンス情報
The SG suffix indicates SnPb/Gold terminal finish, which is NOT RoHS/lead-free compliant. Choose the LG variant (10AS057K4F35E3LG) for RoHS-compliant builds. AEC-Q100 not applicable - this is an FPGA/SoC, not a discrete automotive-grade IC. REACH and conflict-minerals compliance is presumed based on Intel/Altera standard product compliance.