Altera

10AX115U3F45I2LG - Arria 10 GX FPGA, 1.15M LE | Intel | 1932-BGA

部品番号: 10AX115U3F45I2LG ✓ 生産中

在庫あり 1〜3営業日以内に発送

1932-BBGA, FCBGA (F45) 45mm Package 68,857,856 bit (52.99 Mbit) Memory

開始価格 $6600 USD / 個

MOQ: 1 |

価格更新日: 2026-09-05

ボリューム価格

数量	単価	小計
1	$7850	$7,850.00
10	$7450	$74,500.00
100	$7100	$710,000.00
500	$6850	$3,425,000.00
1,000	$6600	$6,600,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

10AX115U3F45I2LG 概要

The Intel (Altera) 10AX115U3F45I2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) integrating 1,150,000 logic elements, 68,857,856 bits of embedded memory, and 480 DSP blocks in a 1932-ball flip-chip BGA (FCBGA) package rated for the industrial temperature range (-40C to +100C). Built on TSMC's 20nm process, this Arria 10 GX device delivers mid-range programmable logic fabric with up to 96 transceiver lanes operating up to 12.5 Gbps and a hardened floating-point DSP block architecture optimized for high-performance signal processing.

An FPGA (Field Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and embedded memory and DSP resources. Unlike an ASIC, an FPGA's function is defined by user-loaded configuration data, enabling rapid hardware iteration, post-deployment upgrades, and hardware-level parallelism. Within the programmable logic hierarchy, FPGAs sit above CPLDs (which are smaller and non-volatile) and below structured ASICs in unit cost; Arria 10 GX specifically targets mid-range transceiver-heavy designs bridging Cyclone and Stratix families.

Key differentiating features of the 10AX115U3F45I2LG include 1,150,000 logic elements (LEs), 427,200 adaptive logic modules (ALMs), 52.99 Mbit embedded memory, 480 DSP blocks, and 24 transceivers at the U3 speed grade (12.5 Gbps). The part ships in a 45mm FCBGA-1932 (F45) package suitable for high-pin-count designs requiring maximum I/O density, and is qualified to the industrial operating range.

Arria 10 GX architecture combines a hard memory controller, PCIe hard IP blocks, and 10/12.5 Gbps transceivers on the same die, allowing deterministic latency and lower power than soft implementations. Compared with previous 28nm Arria V, Arria 10 GX achieves roughly 2x DSP throughput per watt, making it suitable for compute-intensive applications like 4K video processing and wireless baseband.

Typical applications include 4K/8K video broadcast equipment, 100G/400G Ethernet line cards, wireless LTE/5G fronthaul, radar and electronic warfare signal processing, medical imaging accelerators, and high-performance compute offload cards. The U3 speed grade supports up to 12.5 Gbps backplane and chip-to-chip links.

When designing with this device, plan for high-density PCB with 1.0mm BGA pitch, multi-layer PCB stack-up (12+ layers typical), and strict power integrity for the 0.95V core rail. Quartus Prime software provides synthesis, place-and-route, and timing analysis.

This page synthesizes distributor pricing, drop-in Arria 10 alternatives, and practical board-design notes not found in the manufacturer datasheet.

ドロップイン代替品: 10AX115U3F45I2LG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: 10AX115U3F45I2LG （同一形状・フットプリント） — 相違点: Package, Process Technology, DSP Blocks, Operating Temperature, Speed Grade.

10AX115U2F45I2LG

Intel

Package: 1932-ball FCBGA (F45)

Process Technology: 20 nm

DSP Blocks: 1,518

比較対象 10AX115U3F45I2LG →

10AX115U2F45I2SG

Altera

Package: 1932-BBGA, FCBGA (45 x 45 mm)

Process Technology: 20 nm

Operating Temperature: -40C to +100C (TJ)

比較対象 10AX115U3F45I2LG →

10AX115U3F45E2LG

Intel

Process Technology: 20 nm TSMC

DSP Blocks: Variable-precision, 1.5 TFLOPs FP32

Operating Temperature: 0C to +100C (Industrial, E2 grade)

比較対象 10AX115U3F45I2LG →

10AX115U3F45E2SG

Intel

Package: 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch)

DSP Blocks: Variable-precision, hardened floating-point

Operating Temperature: Industrial (junction -40 °C to +100 °C) – device grade U

比較対象 10AX115U3F45I2LG →

✅ ドロップイン

Intel

📦 1932-BBGA, FCBGA (F45) 45mm

Arria 10 GX · 1,150,000 · 427,200 · 68,857,856 (≈ 52.99 Mbit) · 17.4 Gbps · Variable-precision, hardened floating-point · 2 (DDR4/DDR3/QDRII+/RLDRAM3)

✓ 在庫あり

$5800 / 個

データシートを見る →

10AX115U3F45I2LG 最大定格＆電気的特性

Family	Arria 10 GX
Logic Elements	1,150,000 LE
Adaptive Logic Modules (ALMs)	427,200 ALM
Embedded Memory	68,857,856 bit (52.99 Mbit)
DSP Blocks	480
Transceivers	24 (up to 12.5 Gbps, U3 speed grade)
Process Technology	20nm
パッケージ	1932-BBGA, FCBGA (F45) 45mm
動作温度	-40C to +100C (Industrial)
実装タイプ	Surface Mount (BGA)
Packaging	Tray
Configuration Memory	SRAM-based (volatile)
Hard Memory Controllers	Yes
Hard PCIe Blocks	Yes (Gen3)
RoHS ステータス	Compliant

10AX115U3F45I2LG 1932-bbga, fcbga (f45) 45mm ピン配置ガイド

10AX115U3F45I2LG (1932-bbga, fcbga (f45) 45mm パッケージ) のピン配置。このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

10AX115U3F45I2LG の 1932-bbga, fcbga (f45) 45mm パッケージピン配置図

詳細なピン配置データはありません: 10AX115U3F45I2LG.

詳細はデータシートをご参照ください。

主な用途

10AX115U3F45I2LG の用途: 6 件s: 100G/400G Ethernet Line Cards, Wireless 4G/5G Fronthaul CPRI, 4K/8K Video Broadcast Processing, Radar and Electronic Warfare Signal Processing, Medical Imaging (CT/MRI) Reconstruction, High-Performance Compute Offload Cards.

🌐

100G/400G Ethernet Line Cards

The 10AX115U3F45I2LG is well-suited for 100G and aggregate 400G Ethernet line cards in telecom and data-center switching. The U3 speed grade delivers 12.5 Gbps per lane across 24 transceivers for ~300 Gbps aggregate serial bandwidth, while the 1.15M LE fabric absorbs soft-MAC, classification, and packet-processing logic. Its 480 DSP blocks accelerate hashing and crypto offload. Industrial temperature rating allows deployment in NEBS-compliant telecom chassis without thermal derating.

おすすめ

📡

Wireless 4G/5G Fronthaul CPRI

In LTE and 5G fronthaul infrastructure, the 10AX115U3F45I2LG implements CPRI and eCPRI protocols on its 12.5 Gbps transceivers, supporting up to 24 RRH links per device. The 1.15M LE fabric handles PHY-layer baseband processing, while 480 DSP blocks accelerate FFT/iFFT and channelization filters. Hard PCIe Gen3 blocks enable direct host offload. The FCBGA-1932 package integrates cleanly into ATCA and OCP-style baseband cards.

おすすめ

10AX115U3F45E2LG · Intel 10AX115S4F45I3LG · Intel

📺

4K/8K Video Broadcast Processing

The 10AX115U3F45I2LG is widely deployed in 4K and 8K broadcast equipment for real-time video processing, color-space conversion, and multi-stream encoding. The 480 DSP blocks deliver the parallel throughput required for HEVC and AV1 codec acceleration, while 52.99 Mbit of embedded memory buffers reference frames and intermediate line stores. The FCBGA-1932 package supports up to 24 video SERDES channels for SDI/HDMI ingest, fitting a single PCB for video switchers.

おすすめ

10AX115U3F45I2SG · Intel 10AX090U3F45I2LG · Intel

✈️

Radar and Electronic Warfare Signal Processing

Defense radar and EW systems leverage the 10AX115U3F45I2LG's 1.15M LE fabric and 480 DSP blocks for pulse compression, beamforming, and Doppler processing at sample rates up to several hundred MSPS. The 12.5 Gbps transceivers feed digital receiver data into the FPGA from multi-channel ADCs. Industrial temperature and rugged FCBGA-1932 package make the device suitable for airborne and naval platforms when paired with conformal coating and vibration isolation.

おすすめ

10AX115U3F45E2LG · Intel 10AX115R4F40I3LG · Intel

💊

Medical Imaging (CT/MRI) Reconstruction

The 10AX115U3F45I2LG accelerates CT and MRI image reconstruction in the back-end of medical imaging systems. Its 480 DSP blocks execute filtered back-projection and iterative reconstruction kernels, while 52.99 Mbit embedded memory holds projection data. Transceivers aggregate raw RF data from multi-channel detector arrays at 12.5 Gbps per lane. The industrial temperature range supports stable operation in controlled hospital-room environments.

おすすめ

10AX115U2F45I2LG · Intel 10AX090U3F45I2LG · Intel

🖥️

High-Performance Compute Offload Cards

Data-center acceleration cards use the 10AX115U3F45I2LG as a coprocessor for genomics, financial Monte Carlo, and AI inference offload. The PCIe Gen3 hard IP blocks provide low-latency host links, while the 1.15M LE fabric implements custom numeric pipelines. The 480 DSP blocks accelerate floating-point and fixed-point arithmetic at 2-3x the throughput of soft implementations, and 24 transceivers support multi-host configurations or FPGA-to-FPGA clustering.

おすすめ

10AX115U3F45I2SG · Intel 10AX115U3F45E2SG · Intel

おすすめ製品の概要

10AX115U3F45I2SG Intel 使用用途: 100G/400G Ethernet Line Cards, 4K/8K Video Broadcast Processing, High-Performance Compute Offload Cards 10AX115U2F45I2LG Intel 使用用途: 100G/400G Ethernet Line Cards, Medical Imaging (CT/MRI) Reconstruction 10AX115U3F45E2LG Intel 使用用途: Wireless 4G/5G Fronthaul CPRI, Radar and Electronic Warfare Signal Processing 10AX115S4F45I3LG Intel 使用用途: Wireless 4G/5G Fronthaul CPRI 10AX090U3F45I2LG Intel 使用用途: 4K/8K Video Broadcast Processing, Medical Imaging (CT/MRI) Reconstruction 10AX115R4F40I3LG Intel 使用用途: Radar and Electronic Warfare Signal Processing 10AX115U3F45E2SG Intel 使用用途: High-Performance Compute Offload Cards

What is the 10AX115U3F45I2LG?

The 10AX115U3F45I2LG is an Intel (formerly Altera) Arria 10 GX FPGA with 1,150,000 logic elements, 480 DSP blocks, 52.99 Mbit embedded memory, and 24 transceivers rated up to 12.5 Gbps, in a 1932-ball FCBGA package. It is built on TSMC 20nm process and targets transceiver-heavy mid-range applications.

How many logic elements does 10AX115U3F45I2LG have?

The 10AX115U3F45I2LG contains 1,150,000 logic elements (LEs) organized as 427,200 adaptive logic modules (ALMs). This is the largest density in the Arria 10 GX family (the 10AX115 designation), suitable for parallel-processing compute and high-channel-count DSP pipelines.

What is the maximum transceiver speed of 10AX115U3F45I2LG?

According to the Altera Arria 10 GX datasheet, the U3 speed grade transceivers operate up to 12.5 Gbps per channel, supporting protocols such as PCIe Gen3, 10G/40G Ethernet, CPRI, and JESD204B. The device has 24 transceiver channels in this package variant.

What package does the 10AX115U3F45I2LG use?

The 10AX115U3F45I2LG ships in a 1932-ball flip-chip BGA (FCBGA), package code F45, measuring 45mm square with 1.0mm ball pitch. This high-density package is required for the 24 transceivers and 480 DSP blocks and demands a multi-layer PCB stack-up.

What software is used to program 10AX115U3F45I2LG?

The 10AX115U3F45I2LG is programmed using Intel Quartus Prime Pro Edition (version 17.0 or later for Arria 10). Quartus Prime provides synthesis, place-and-route, timing closure, and the Platform Designer system-integration tool. The Arria 10 GX family supports partial reconfiguration.

What is the price of 10AX115U3F45I2LG?

As of 2026-09-05, the 10AX115U3F45I2LG lists at approximately $7,850 USD per unit on DigiKey for qty-1. Pricing breaks to about $7,100 at qty-100 and $6,600 at qty-1000. Octopart confirms availability from authorized distributors; lead time is typically 8-12 weeks.

Where can I buy 10AX115U3F45I2LG?

The 10AX115U3F45I2LG is available from authorized distributors including DigiKey (DigiKey part number 5429525), Mouser, and Intel direct. The Altera product page lists additional regional distributors. Counterfeit risk is high for FPGAs of this value; always source through authorized channels.

What is the lead time for 10AX115U3F45I2LG?

Lead time for the 10AX115U3F45I2LG is typically 8-12 weeks when ordered through authorized distributors as of 2026-09-05. Intel direct orders may carry longer lead times but provide better lot traceability. Stock at major distributors fluctuates; check live inventory before committing.

Is the 10AX115U3F45I2LG in stock?

Stock availability for 10AX115U3F45I2LG varies; as of 2026-09-05, DigiKey lists it with a 'ships today' badge, while Mouser reports limited qty. For volume orders above 100 units, contact Intel direct or authorized distributors 6-8 weeks before required date.

10AX115U3F45I2LG vs 10AX115U2F45I2LG - which is faster?

The 10AX115U3F45I2LG is the U3 speed grade (12.5 Gbps transceivers), while 10AX115U2F45I2LG is U2 (up to 10 Gbps). Both share the same 1.15M LE fabric and FCBGA-1932 F45 package. Choose U3 for 10G/40G Ethernet and PCIe Gen3; choose U2 if the design does not need >10 Gbps.

What is the best drop-in replacement for 10AX115U3F45I2LG?

The closest drop-in replacement is 10AX115U3F45I2SG (commercial 0-100C variant), which shares the same F45 FCBGA-1932 footprint and pinout. For an industrial-grade pin-compatible alternative, 10AX115U3F45E2LG (E3 speed grade) is available but slightly lower performance.

Where to download 10AX115U3F45I2LG datasheet PDF?

The official Arria 10 GX family datasheet can be downloaded from the Intel FPGA documentation portal (intel.com/content/www/us/en/docs/programmable/683846/current/arria-10-overview.html) or via the Altera product page linked in the data_sources section of this page.

Where is the 10AX115U3F45I2LG pinout?

Pin assignments for the 10AX115U3F45I2LG are documented in the Arria 10 GX pin-out file (PDF/CSV), available in the Intel FPGA documentation library. For the F45 package, ball coordinates use Intel's standard alphanumeric grid; Quartus Prime pin planner can import the pinout CSV directly.

Is 10AX115U3F45I2LG suitable for 100G Ethernet designs?

Yes, the 10AX115U3F45I2LG supports 100G Ethernet using multiple 10.3125 Gbps or 12.5 Gbps transceivers aggregated via soft MAC and 100G hard IP blocks. For 400G designs, multiple Arria 10 GX FPGAs or a Stratix 10 variant is required, as 24 transceivers at 12.5 Gbps provide 300 Gbps aggregate bandwidth.

What is the operating temperature range of 10AX115U3F45I2LG?

According to the part number suffix, the 10AX115U3F45I2LG is rated for industrial temperature range, -40C to +100C junction. The 'I' in 'I2LG' indicates industrial; for extended (-40C to +125C) use, the E-grade (10AX115U3F45E2LG) variant is required.

エンジニアリング参考データ: 10AX115U3F45I2LG — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the 10AX115U3F45I2LG when your design requires the U3 speed grade transceivers (12.5 Gbps) and must operate across the full industrial temperature range (-40C to +100C), such as in telecom line cards, industrial automation, or defense platforms. For commercial-grade deployment in studio or data-center air-cooled environments, choose 10AX115U3F45I2SG as a pin-compatible alternative at lower cost. For designs that do not exceed 10 Gbps per lane and need industrial temp, the 10AX115U2F45I2LG is a cost-optimized alternative in the same FCBGA-1932 F45 footprint. All five drop-in alternatives share the same FCBGA-1932 package and pinout, so PCB layout is portable across the family.

代替品との比較

パラメータ	この製品	10AX115U3F45I2SG	10AX115U3F45E2LG	10AX115U2F45I2LG
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Package	FCBGA-1932 (F45) 45mm	FCBGA-1932 (F45) 45mm - same	FCBGA-1932 (F45) 45mm - same	FCBGA-1932 (F45) 45mm - same
Logic Elements	1,150,000 LE	1,150,000 LE	1,150,000 LE	1,150,000 LE
Speed Grade	U3 (12.5 Gbps transceivers)	U3 (12.5 Gbps)	U3, extended temp E-grade	U2 (10 Gbps transceivers)
Temperature Range	Industrial -40C to +100C	Commercial 0C to +100C	Industrial with extended +125C	Industrial -40C to +100C
DSP Blocks	480	480	480	480
Embedded Memory	52.99 Mbit	52.99 Mbit	52.99 Mbit	52.99 Mbit
Transceivers	24 channels up to 12.5 Gbps	24 channels up to 12.5 Gbps	24 channels up to 12.5 Gbps	24 channels up to 10 Gbps

主な差別化要因

U3 speed grade enables 12.5 Gbps transceivers for 100G Ethernet （vs 10AX115U2F45I2LG)
Industrial -40C to +100C temperature range （vs 10AX115U3F45I2SG)
Largest density (1.15M LE) in Arria 10 GX family （vs 10AX090U3F45I2LG)

設計ノート

Estimated: The 10AX115U3F45I2LG typically dissipates 25-40W in a fully utilized configuration with active transceivers and DSP. The FCBGA-1932 F45 package requires a high-performance thermal solution - 4-6 W/mK thermal interface material, a copper or aluminum heatsink with at least 2 C/W resistance, and 400+ LFM airflow. Junction-to-ambient (theta_JA) without airflow is approximately 8 C/W per Altera thermal guidelines.

The 1.0mm pitch FCBGA-1932 requires a 12+ layer PCB with stacked micro-via (laser-drilled) build-up layers. Escape routing uses 4/4 mil trace-and-space in the inner ball-pitch region. A continuous GND plane below the FPGA package and a dedicated 0.95V core power plane are mandatory for power integrity. Decoupling requires ~80 capacitors (0.1uF, 1uF, 10uF, 47uF) within 100 mils of the BGA balls.

Core voltage is 0.95V (VCC) with tolerance +/- 30mV; transceivers use 1.0V and 1.5V auxiliary supplies, with I/O banks at 1.2V-3.3V depending on bank assignment. Power sequencing per Intel Arria 10 guidelines requires VCC to ramp before VCCPT and VCCAUX. Use the Arria 10 power tree with PWM controllers such as LTM4677 or ISL8225MEVAL. Estimated: full-power rails at 50-60W peak.

Transceiver channels operating at 12.5 Gbps require controlled-impedance routing (100 ohm differential +/- 10%) with maximum length matching within 5 mils across all 24 channels. Loss budget must stay under 6 dB at 6.25 GHz Nyquist. Use Megtron 6 or equivalent low-loss dielectric for the transceiver layer, and follow Intel Arria 10 GX PCB designer checklist.

Common pitfalls: (1) Insufficient thermal relief causes thermal shutdown at full load. (2) Configuration errors when JTAG and EPCQ flash are both attached - use MSEL pin resistors correctly per datasheet. (3) Voltage rails not sequencing per spec damages internal logic. (4) Ignoring the partial reconfiguration voltage (VCCP) connection on F45 package variants.