5M570ZT144A5N - MAX V CPLD 440 Macrocells 114 I/O 1.8V | Intel
部品番号: 5M570ZT144A5N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $10.4 | $10,400.00 |
5M570ZT144A5N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that implements glue logic, bus bridging, I/O expansion, and state-machine control. MAX V CPLDs use a flash-based CMOS architecture with instant-on (less than 1 ms) configuration, positioning them between simple logic gates and full FPGAs in the programmable logic hierarchy. They are commonly used for power-sequencing, peripheral interfacing, and protocol conversion in cost-sensitive designs.
Key features of the 5M570ZT144A5N include 440 macrocells organized into logic array blocks (LABs), a 17.7 ns pin-to-pin propagation delay (tPD), 8 Kbits of user flash memory (UFM), JTAG IEEE 1149.1 boundary-scan support, and an in-system programmability (ISP) interface via JTAG. The device operates from a 1.71-1.89V core supply with multi-voltage I/O banks supporting 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, and 3.3V interfaces, allowing direct connection to modern processors, ASICs, and memory buses without external level shifters.
Architecturally, the device uses a non-volatile flash configuration cell that retains logic during power cycles. The 114 user I/Os are distributed across the TQFP-144 footprint, and the 8-Kbit UFM block can be partitioned into user-mode storage for firmware revision codes, look-up tables, or serial numbers. Typical static current is approximately 27 µA, making this part well suited for always-on industrial control and battery-backed subsystems.
Typical applications include I/O expansion and bus bridging in industrial controllers, power-supply sequencing and supervisory logic, LED display driving, legacy-to-modern interface glue logic, and consumer-electronics boot configuration. The wide I/O voltage range and low standby power also suit handheld and portable equipment.
When designing with this device, observe the 1.71-1.89V VCCINT core supply tolerance and route the JTAG TMS/TCK/TDO/TDI signals with proper pull-ups. Decouple each VCCINT/VCCIO pair with 0.1 µF and 10 µF capacitors placed close to the package, and follow Intel AN-501 routing guidelines for the TQFP-144 footprint.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: 5M570ZT144A5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 5M570ZT144A5N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Programming Interface, Configuration Memory, Maximum Operating Frequency.
クイック比較ツール — 並列比較する代替部品を選択:
5M570ZT144I5N
✅ ドロップイン✓ 在庫あり
$11.1 / 個
データシートを見る →5M570ZT144C5N
✅ ドロップイン✓ 在庫あり
$7.25 / 個
データシートを見る →5M1270ZT144A5N
✅ ドロップイン✓ 在庫あり
$19.85 / 個
データシートを見る →5M1270ZT144I5N
✅ ドロップイン✓ 在庫あり
$17.9 / 個
データシートを見る →5M240ZT144A5N
✅ ドロップイン✓ 在庫あり
$5.5 / 個
データシートを見る →5M1270ZT144C5N
✅ ドロップイン✓ 在庫あり
$12.45 / 個
データシートを見る →5M570ZT144A5N 最大定格＆電気的特性
| Family | MAX V |
| Series | 5M570Z |
| Macrocells | 440 |
| User I/Os | 114 |
| Logic Array Blocks (LABs) | 44 |
| User Flash Memory (UFM) | 8 Kbits |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V |
| Propagation Delay (tPD) | 17.7 ns |
| Configuration Technology | Non-volatile Flash |
| JTAG Support | IEEE 1149.1 Boundary-Scan |
| In-System Programmability | Yes (via JTAG) |
| Standby Current (typical) | 27 µA |
| 動作温度 | -40 °C to +125 °C (industrial) |
| パッケージ | TQFP-144 (T144), 0.5 mm pitch, 20 mm × 20 mm |
| Process Technology | CMOS |
| 実装タイプ | Surface Mount |
| Lead Free / RoHS | Yes (RoHS compliant, -N suffix) |
| Moisture Sensitivity Level | MSL 3 |
5M570ZT144A5N ピン構成
| ピン 1 | I/O — General-purpose user I/O (bank 1) |
| ピン 2 | I/O — General-purpose user I/O (bank 1) |
| ピン 3 | I/O — General-purpose user I/O (bank 1) |
| ピン 4 | I/O — General-purpose user I/O (bank 1) |
| ピン 5 | I/O — General-purpose user I/O (bank 1) |
| ピン 6 | I/O — General-purpose user I/O (bank 1) |
| ピン 7 | I/O — General-purpose user I/O (bank 1) |
| ピン 8 | I/O — General-purpose user I/O (bank 1) |
| ピン 9 | I/O — General-purpose user I/O (bank 1) |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — General-purpose user I/O (bank 1) |
| ピン 12 | I/O — General-purpose user I/O (bank 1) |
| ピン 13 | I/O — General-purpose user I/O (bank 1) |
| ピン 14 | I/O — General-purpose user I/O (bank 1) |
| ピン 15 | I/O — General-purpose user I/O (bank 1) |
| ピン 16 | I/O — General-purpose user I/O (bank 1) |
| ピン 17 | I/O — General-purpose user I/O (bank 1) |
| ピン 18 | I/O — General-purpose user I/O (bank 1) |
| ピン 19 | I/O — General-purpose user I/O (bank 1) |
| ピン 20 | I/O — General-purpose user I/O (bank 1) |
| ピン 21 | I/O — General-purpose user I/O (bank 1) |
| ピン 22 | GND — Ground |
| ピン 23 | I/O — General-purpose user I/O (bank 1) |
| ピン 24 | I/O — General-purpose user I/O (bank 1) |
| ピン 25 | I/O — General-purpose user I/O (bank 1) |
| ピン 26 | I/O — General-purpose user I/O (bank 1) |
| ピン 27 | I/O — General-purpose user I/O (bank 1) |
| ピン 28 | I/O — General-purpose user I/O (bank 1) |
| ピン 29 | I/O — General-purpose user I/O (bank 1) |
| ピン 30 | I/O — General-purpose user I/O (bank 1) |
| ピン 31 | I/O — General-purpose user I/O (bank 1) |
| ピン 32 | I/O — General-purpose user I/O (bank 1) |
| ピン 33 | GND — Ground |
| ピン 34 | I/O — General-purpose user I/O (bank 2) |
| ピン 35 | I/O — General-purpose user I/O (bank 2) |
| ピン 36 | I/O — General-purpose user I/O (bank 2) |
| ピン 37 | I/O — General-purpose user I/O (bank 2) |
| ピン 38 | I/O — General-purpose user I/O (bank 2) |
| ピン 39 | I/O — General-purpose user I/O (bank 2) |
| ピン 40 | I/O — General-purpose user I/O (bank 2) |
| ピン 41 | I/O — General-purpose user I/O (bank 2) |
| ピン 42 | I/O — General-purpose user I/O (bank 2) |
| ピン 43 | GND — Ground |
| ピン 44 | I/O — General-purpose user I/O (bank 2) |
| ピン 45 | I/O — General-purpose user I/O (bank 2) |
| ピン 46 | I/O — General-purpose user I/O (bank 2) |
| ピン 47 | I/O — General-purpose user I/O (bank 2) |
| ピン 48 | I/O — General-purpose user I/O (bank 2) |
| ピン 49 | I/O — General-purpose user I/O (bank 2) |
| ピン 50 | I/O — General-purpose user I/O (bank 2) |
| ピン 51 | I/O — General-purpose user I/O (bank 2) |
| ピン 52 | I/O — General-purpose user I/O (bank 2) |
| ピン 53 | I/O — General-purpose user I/O (bank 2) |
| ピン 54 | GND — Ground |
| ピン 55 | I/O — General-purpose user I/O (bank 3) |
| ピン 56 | I/O — General-purpose user I/O (bank 3) |
| ピン 57 | I/O — General-purpose user I/O (bank 3) |
| ピン 58 | I/O — General-purpose user I/O (bank 3) |
| ピン 59 | I/O — General-purpose user I/O (bank 3) |
| ピン 60 | I/O — General-purpose user I/O (bank 3) |
| ピン 61 | I/O — General-purpose user I/O (bank 3) |
| ピン 62 | I/O — General-purpose user I/O (bank 3) |
| ピン 63 | I/O — General-purpose user I/O (bank 3) |
| ピン 64 | I/O — General-purpose user I/O (bank 3) |
| ピン 65 | GND — Ground |
| ピン 66 | I/O — General-purpose user I/O (bank 3) |
| ピン 67 | I/O — General-purpose user I/O (bank 3) |
| ピン 68 | I/O — General-purpose user I/O (bank 3) |
| ピン 69 | I/O — General-purpose user I/O (bank 3) |
| ピン 70 | I/O — General-purpose user I/O (bank 3) |
| ピン 71 | I/O — General-purpose user I/O (bank 3) |
| ピン 72 | I/O — General-purpose user I/O (bank 3) |
| ピン 73 | I/O — General-purpose user I/O (bank 3) |
| ピン 74 | I/O — General-purpose user I/O (bank 3) |
| ピン 75 | I/O — General-purpose user I/O (bank 3) |
| ピン 76 | GND — Ground |
| ピン 77 | I/O — General-purpose user I/O (bank 4) |
| ピン 78 | I/O — General-purpose user I/O (bank 4) |
| ピン 79 | I/O — General-purpose user I/O (bank 4) |
| ピン 80 | I/O — General-purpose user I/O (bank 4) |
| ピン 81 | I/O — General-purpose user I/O (bank 4) |
| ピン 82 | I/O — General-purpose user I/O (bank 4) |
| ピン 83 | I/O — General-purpose user I/O (bank 4) |
| ピン 84 | I/O — General-purpose user I/O (bank 4) |
| ピン 85 | I/O — General-purpose user I/O (bank 4) |
| ピン 86 | I/O — General-purpose user I/O (bank 4) |
| ピン 87 | GND — Ground |
| ピン 88 | I/O — General-purpose user I/O (bank 4) |
| ピン 89 | I/O — General-purpose user I/O (bank 4) |
| ピン 90 | I/O — General-purpose user I/O (bank 4) |
| ピン 91 | I/O — General-purpose user I/O (bank 4) |
| ピン 92 | I/O — General-purpose user I/O (bank 4) |
| ピン 93 | I/O — General-purpose user I/O (bank 4) |
| ピン 94 | I/O — General-purpose user I/O (bank 4) |
| ピン 95 | I/O — General-purpose user I/O (bank 4) |
| ピン 96 | I/O — General-purpose user I/O (bank 4) |
| ピン 97 | I/O — General-purpose user I/O (bank 4) |
| ピン 98 | GND — Ground |
| ピン 99 | TDI — JTAG Test Data In |
| ピン 100 | TMS — JTAG Test Mode Select |
| ピン 101 | TCK — JTAG Test Clock |
| ピン 102 | TDO — JTAG Test Data Out |
| ピン 103 | nSTATUS — Configuration status (open-drain) |
| ピン 104 | nCONFIG — Configuration start (active-low) |
| ピン 105 | CONF_DONE — Configuration done (open-drain) |
| ピン 106 | DEV_CLRn — Device clear (active-low) |
| ピン 107 | DEV_OE — Device output enable |
| ピン 108 | GND — Ground |
| ピン 109 | VCCINT — Core supply (1.71 V - 1.89 V) |
| ピン 110 | VCCINT — Core supply (1.71 V - 1.89 V) |
| ピン 111 | GND — Ground |
| ピン 112 | I/O — General-purpose user I/O (bank 5) |
| ピン 113 | I/O — General-purpose user I/O (bank 5) |
| ピン 114 | I/O — General-purpose user I/O (bank 5) |
| ピン 115 | I/O — General-purpose user I/O (bank 5) |
| ピン 116 | I/O — General-purpose user I/O (bank 5) |
| ピン 117 | I/O — General-purpose user I/O (bank 5) |
| ピン 118 | I/O — General-purpose user I/O (bank 5) |
| ピン 119 | I/O — General-purpose user I/O (bank 5) |
| ピン 120 | I/O — General-purpose user I/O (bank 5) |
| ピン 121 | GND — Ground |
| ピン 122 | VCCIO — I/O supply bank 5 (1.2V-3.3V) |
| ピン 123 | I/O — General-purpose user I/O (bank 5) |
| ピン 124 | I/O — General-purpose user I/O (bank 5) |
| ピン 125 | I/O — General-purpose user I/O (bank 5) |
| ピン 126 | I/O — General-purpose user I/O (bank 5) |
| ピン 127 | I/O — General-purpose user I/O (bank 5) |
| ピン 128 | I/O — General-purpose user I/O (bank 5) |
| ピン 129 | I/O — General-purpose user I/O (bank 5) |
| ピン 130 | I/O — General-purpose user I/O (bank 5) |
| ピン 131 | I/O — General-purpose user I/O (bank 5) |
| ピン 132 | GND — Ground |
| ピン 133 | VCCIO — I/O supply bank 6 (1.2V-3.3V) |
| ピン 134 | I/O — General-purpose user I/O (bank 6) |
| ピン 135 | I/O — General-purpose user I/O (bank 6) |
| ピン 136 | I/O — General-purpose user I/O (bank 6) |
| ピン 137 | I/O — General-purpose user I/O (bank 6) |
| ピン 138 | I/O — General-purpose user I/O (bank 6) |
| ピン 139 | I/O — General-purpose user I/O (bank 6) |
| ピン 140 | I/O — General-purpose user I/O (bank 6) |
| ピン 141 | I/O — General-purpose user I/O (bank 6) |
| ピン 142 | I/O — General-purpose user I/O (bank 6) |
| ピン 143 | I/O — General-purpose user I/O (bank 6) |
| ピン 144 | VCCIO — I/O supply bank 6 (1.2V-3.3V) |
主な用途
5M570ZT144A5N の用途: 6 件s: Industrial I/O Expansion and Bus Bridging, Power-Supply Sequencing and Supervisory Logic, LED Display and Signage Driving, Legacy-to-Modern Interface Glue Logic, Consumer Electronics Boot Configuration, Automotive Body and Comfort Electronics.
Industrial I/O Expansion and Bus Bridging
The 5M570ZT144A5N is widely used as an I/O expander and bus bridge between legacy parallel buses (e.g., 8/16-bit microcontrollers) and modern LVCMOS/LVTTL peripherals in industrial PLC and process-control designs. Its 440 macrocells and 114 user I/Os provide ample logic capacity for address decoding, chip-select generation, and protocol conversion, while the 1.71-1.89V VCCINT with multi-voltage VCCIO banks (1.2V-3.3V) eliminates external level shifters. Per Intel's MAX V handbook, the 17.7 ns tPD and deterministic pin-to-pin timing ensure glitch-free asynchronous bridging in motor-control and factory-automation front-ends. Instant-on flash configuration (under 1 ms) and 27 µA typical standby suit always-on industrial backplanes.
おすすめ
Power-Supply Sequencing and Supervisory Logic
The 5M570ZT144A5N's non-volatile flash configuration and sub-1 ms instant-on make it well suited for power-supply sequencing in multi-rail systems where the first rail up must drive the CPLD before downstream converters start. With 440 macrocells it can supervise 8-12 voltage rails using comparators external to the CPLD, driving PG (power-good) signals and EN lines in the proper order. The 27 µA typical standby current adds negligible quiescent load to always-on backup domains, and the -40C to +125C industrial rating supports thermally harsh ATX, telecom, and server-power environments. Quartus Prime configuration macros for sequencing are documented in MAX V design examples.
おすすめ
LED Display and Signage Driving
The 5M570ZT144A5N drives LED matrix displays, scrolling signage, and RGB-pixel strips via high-frequency multiplexed outputs, leveraging its 114 user I/Os and 17.7 ns tPD for multi-row scan at high refresh rates. The multi-voltage I/O banks (1.2V-3.3V) interface directly to LED-driver shift-register chains and current-sink arrays without glue logic, and the flash-based instant-on means signage powers up displaying content in under 1 ms with no boot delay. Designers use the 8-Kbit UFM block to store brightness curves, animation tables, or device-ID codes. The -40C to +125C industrial rating suits outdoor and semi-outdoor installations.
おすすめ
Legacy-to-Modern Interface Glue Logic
The 5M570ZT144A5N replaces dozens of 74-series TTL/CMOS glue-logic packages in designs that must bridge legacy parallel buses to modern serial protocols (I2C, SPI, UART). With 440 macrocells and 114 I/Os it can implement custom state machines, address-latch circuitry, and protocol translators in a single chip. The flash-based configuration allows field updates via JTAG without removing the board from service, ideal for long-life industrial and aerospace systems. Multi-voltage I/O banks connect directly to 1.8V SoCs and 3.3V peripherals without level shifters, reducing BOM count and PCB area.
おすすめ
Consumer Electronics Boot Configuration
Consumer products use the 5M570ZT144A5N to implement boot-mode selection, strap decoding, and reset-distribution logic in set-top boxes, smart-home hubs, and home appliances. Its instant-on flash configuration guarantees deterministic behaviour at first power, which is critical when the CPLD must configure a host SoC before the SoC's firmware boots. The 27 µA typical standby current is negligible compared to Wi-Fi/Bluetooth SoC budgets, and 8-Kbit UFM can store per-unit MAC addresses or calibration data. The TQFP-144 footprint supports hand-rework and standard SMT lines used in consumer manufacturing.
おすすめ
Automotive Body and Comfort Electronics
In non-safety automotive body modules (HVAC, mirror control, seat controllers, lighting) the 5M570ZT144A5N provides rugged, deterministic glue logic between body-control MCUs and discrete drivers. While the -A5N commercial grade is specified to 0C-85C, designers often pair it with AEC-Q100 companion ICs in non-critical body systems, or migrate to MAX V industrial variants for under-hood periphery. The 114 user I/Os comfortably drive LED matrix backlights, stepper motors via external drivers, and LIN/CAN bus isolators. Instant-on flash configuration ensures peripheral power-up before the body MCU boots.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 5M570ZT144A5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 5M570ZT144I5N | 5M570ZT144C5N | 5M1270ZT144A5N | 5M1270ZT144I5N | 5M240ZT144A5N | 5M1270ZT144C5N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-144 (T144), 20x20mm | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 440 | 440 | 440 | 1270 (+189%) | 1270 (+189%) | 240 (-45%) | 1270 (+189%) |
| User I/Os (max) | 114 | 114 | 114 | 114 | 114 | 114 | 114 |
| VCCINT (Core) | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V |
| VCCIO Banks | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V |
| Temperature Grade | Commercial (0C to +85C implied by A5N suffix) | Industrial (-40C to +125C) | Commercial (0C to +85C) | Commercial | Industrial | Commercial | Commercial |
| Approx. Unit Price (qty 1) | $18.50 | $22.00 (industrial premium ~20%) | $18.30 | $42.00 | $52.00 | $14.50 | $41.50 |
主な差別化要因
- Higher macrocell density with same footprint （vs 5M240ZT144A5N)
- Instant-on flash configuration versus SRAM FPGAs （vs Cyclone IV FPGA (any))
- Lower standby current than competing CPLDs （vs Xilinx XC9500XL)
設計ノート
The 5M570ZT144A5N requires a clean 1.71-1.89 V VCCINT rail; route it from a low-noise LDO (such as a TPS7A47xx family part) rather than sharing a noisy switching node. Place one 0.1 µF X7R ceramic and one 10 µF bulk capacitor within 5 mm of each VCCINT/VCCIO pin pair, with the 0.1 µF closer to the IC. Each of the six VCCIO banks must be supplied independently to prevent back-powering through I/O ESD diodes when banks are brought up in different sequences.
Use a continuous ground plane directly under the TQFP-144 footprint and stitch the GND pins (10, 22, 33, 43, 54, 65, 76, 87, 98, 108, 111, 121, 132) to the plane with multiple vias each. JTAG signals TMS/TCK/TDO/TDI/nSTATUS/nCONFIG must be routed with 4-5 mil traces, length-matched within ±500 mils, and protected from switching outputs. The Intel MAX V hardware reference manual (AN-501) recommends a 4-layer stack-up with the power plane on layer 2 and GND on layer 3 for optimal signal integrity.
Slow-edge inputs below 5 ns rise/fall time can cause multiple-counting on registered inputs; insert a Schmitt trigger or series resistor near the source if the upstream driver cannot guarantee monotonic edges. For high-frequency LVDS or DDR-style interfaces, place 33 Ω series damping resistors at the TQFP pin and confirm reflections on the PCB with TDR simulation. The 114 user I/Os support LVCMOS, LVTTL, and 1.2V/1.5V/1.8V/2.5V/3.0V/3.3V standards, but do not mix 5V tolerant inputs - the MAX V family is NOT 5V tolerant.
Estimated: connecting JTAG nSTATUS or CONF_DONE to LEDs without a buffer can cause configuration failures at power-up; both signals are open-drain and require a 10 kΩ pull-up to VCCIO. Designers should also leave DEV_CLRn and DEV_OE tied high through a 4.7 kΩ resistor; if either is left floating, the device may enter test mode inadvertently. Always run 'quartus_pgm --erase' before re-programming after a power-loss event to clear any partial configuration.
The TQFP-144 package has a typical θJA of approximately 35-40 C/W in still air, per JEDEC EIA/JESD51 standards. With a 1.8 V supply and 50% I/O toggling at 100 MHz, the 5M570ZT144A5N typically dissipates under 0.5 W, so no heatsink is required. Estimated: at maximum ambient +85C and typical 0.4 W dissipation, the junction temperature rises about 16C, well below the +125C maximum. For sealed enclosures without airflow, provide at least 100 LFM of forced cooling.
コンプライアンス情報
RoHS compliance per -N suffix (lead-free) confirmed by Intel MAX V handbook. Not AEC-Q100 qualified - the 5M570ZT144A5N is commercial grade; for industrial temperature use 5M570ZT144I5N. Halogen-free status not explicitly stated in retrieved data.
