5M80ZM68I5N - 64 Macrocell MAX V CPLD, 68-BGA, Industrial | Intel
部品番号: 5M80ZM68I5N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.41 | $6.41 |
| 10 | $5.95 | $59.50 |
| 100 | $5.2 | $520.00 |
| 500 | $4.62 | $2,310.00 |
| 1,000 | $4.15 | $4,150.00 |
5M80ZM68I5N 概要
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic IC that integrates multiple macrocell-based logic blocks (LABs) with a programmable interconnect matrix. CPLDs sit alongside FPGAs in the broader programmable logic hierarchy (programmable logic device -> CPLD -> programmable logic -> digital IC) and are typically chosen over FPGAs for glue-logic, bus-interface bridging, power-sequencing, and high-drive I/O expansion tasks where deterministic timing and zero-configuration-boot behavior matter more than raw logic density.
Key features of the 5M80ZM68I5N include 64 macrocells across 4 logic array blocks, 160 user-flash-memory bits for user-defined storage, an internal oscillator, JTAG (IEEE 1149.1) and in-system programmability via the Altera/Intel Quartus Prime design tool, and a user-mode flash block for customer IP or revision identification. The device integrates a voltage regulator that derives the 1.8 V core from a user-supplied VCCIO or VCCINT rail, simplifying board power design.
Architecturally, the MAX V CPLD uses a classic AND-OR PLA fabric with each macrocell containing a programmable AND array, a flip-flop, product-term steering, and a selectable I/O standard. The 68-BGA package exposes up to 52 user I/O pins (52-MBGA variants differ in I/O count) and offers very small board footprint compared to equivalent TQFP-100 CPLDs.
Typical applications include I/O expansion and level shifting between 1.8 V MCUs and 3.3 V peripherals, bus-interface bridging (for example I2C, SPI, UART, or parallel memory glue), power-sequence and reset-distribution controllers in industrial control boards, and consumer/automotive infotainment subsystems where instant-on non-volatile logic is required at low cost.
When designing with this device, allocate a 0.1 uF + 1 uF decoupling network on every VCCIO bank and place the JTAG TMS/TCK/TDO/TDI chain within 75 mm of the BGA balls to keep programming reliable. Use Quartus Prime 15.1 or later with the MAX V device support installed to generate JIC/POF programming files.
ドロップイン代替品: 5M80ZM68I5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 5M80ZM68I5N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Configuration Memory, Logic Elements, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
5M80ZM68C5N
✅ ドロップイン✓ 在庫あり
$1.74 / 個
データシートを見る →5M80ZM68C4N
✅ ドロップイン✓ 在庫あり
$2.52 / 個
データシートを見る →5M80ZM68A5N
✅ ドロップイン✓ 在庫あり
$2.8 / 個
データシートを見る →5M160ZM68I5N
✅ ドロップイン✓ 在庫あり
$6.8 / 個
データシートを見る →5M240ZM68I5N
✅ ドロップイン✓ 在庫あり
$1.25 / 個
データシートを見る →5M80ZM68I5N 最大定格＆電気的特性
| Family | MAX V |
| Macro Cells | 64 |
| Logic Array Blocks (LABs) | 4 |
| Maximum Operating Frequency | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns |
| User I/O Pins | 52 |
| User Flash Memory | 160 bits |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| パッケージ | 68-ball MBGA (5M80ZM68) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +100C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) + ISP |
| Operating Mode | Non-volatile, instant-on |
| RoHS ステータス | Compliant |
| Lead-Free / Halogen-Free | Yes / Unknown |
5M80ZM68I5N 68-ball mbga (5m80zm68) ピン配置ガイド
5M80ZM68I5N (68-ball mbga (5m80zm68) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 5M80ZM68I5N.
詳細は データシート をご参照ください。
主な用途
5M80ZM68I5N の用途: 6 件s: I/O Expansion and Level Shifting, Bus Interface Bridging (I2C / SPI / UART / Parallel), Power Sequencing and Reset Distribution, Industrial Control and Factory Automation, Consumer / Automotive Infotainment Subsystems, Communications and Telecom Peripherals.
I/O Expansion and Level Shifting
The 5M80ZM68I5N's four independent VCCIO banks (1.2 V to 3.3 V) make it ideal for I/O expansion between a 1.8 V MCU and 3.3 V peripheral devices. Place the CPLD between the MCU bus and the peripherals; each I/O pin drives at the bank voltage, eliminating external level-shifters. The 52 user I/Os and 64 macrocells fit 30-50 glue-logic equations, while the 7.5 ns tPD guarantees deterministic glue-logic timing for SPI, I2C, UART, and parallel memory bridges.
おすすめ
Bus Interface Bridging (I2C / SPI / UART / Parallel)
MAX V CPLDs are widely deployed as protocol bridges between mismatched bus widths, voltages, or clock domains. The 5M80ZM68I5N can translate an 8-bit parallel bus to SPI, isolate two I2C buses with different addresses, or convert a 3.3 V UART to 1.8 V logic in a single chip. Its non-volatile instant-on configuration (under 1 ms from power-up) is critical for systems that boot in a defined state without firmware load. The 7.5 ns propagation delay supports bridges up to ~80 MHz.
おすすめ
Power Sequencing and Reset Distribution
The 5M80ZM68I5N is well-suited for power-rail sequencing in multi-supply systems. Program the CPLD to assert DC-DC EN pins in a defined order with software-tunable delays using the internal oscillator and counter macrocells. With 1.8 V core operation, it can be powered by the same rail that it sequences, simplifying the start-up dependency chain. Its industrial -40C to +100C grade makes it ideal for factory-automation controllers and outdoor telecom equipment.
おすすめ
Industrial Control and Factory Automation
PLC-style controllers, motor-driver front-ends, and sensor aggregators benefit from the 5M80ZM68I5N's industrial temperature rating and instant-on non-volatile behavior. The CPLD can debounce mechanical switch inputs, generate deterministic PWM for stepper motor control up to ~100 kHz, and aggregate SSI-encoder data into a parallel bus. Its 1.8 V core plus wide VCCIO tolerates the noisy factory-floor environment when paired with proper decoupling (0.1 uF + 1 uF per bank).
おすすめ
Consumer / Automotive Infotainment Subsystems
Dashboard peripherals, HVAC controllers, and audio DSP front-ends often need a non-volatile, deterministic state machine to manage button-matrix scanning, LED driving, and I2S/SAI stream routing. The 5M80ZM68I5N provides instant-on logic without external boot Flash, runs from 1.8 V, and the 68-ball MBGA fits into compact 5x5 mm PCB layouts. Designers select this part when their state-machine and glue-logic fits within 64 macrocells and they need industrial temperature grade for cabin-mount reliability.
おすすめ
Communications and Telecom Peripherals
CPE routers, fiber-optic line cards, and base-station peripherals use the 5M80ZM68I5N for clock-domain crossing, front-panel LED and button scanning, and low-speed serial multiplexing. The 52 user I/Os comfortably drive up to 6 front-panel LEDs via current-limit resistors and serve as glue logic between a PHY, an FPGA, and a host CPU. The industrial temperature grade, IEEE 1149.1 JTAG chain, and Quartus Prime design flow make this part a telecom-bench standard.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 5M80ZM68I5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 5M80ZM68C5N | 5M80ZM68C4N | 5M80ZM68A5N | 5M160ZM68I5N | 5M240ZM68I5N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 68-ball MBGA | 68-ball MBGA (same) | 68-ball MBGA (same) | 68-ball MBGA (same) | 68-ball MBGA (same) | 68-ball MBGA (same) |
| Macro Cells | 64 | 64 | 64 | 64 | 160 | 240 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns (similar) | Slower (C4 grade) | Comparable A-speed | 7.5 ns | 7.5 ns |
| User I/O Pins | 52 | 52 | 52 | 52 | 52 | 52 |
| Pin-to-Pin Compatible | Yes (reference) | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) | Yes (drop-in upgrade) | Yes (drop-in upgrade) |
| Programming Interface | JTAG (IEEE 1149.1) + ISP | JTAG + ISP | JTAG + ISP | JTAG + ISP | JTAG + ISP | JTAG + ISP |
主な差別化要因
- Non-volatile instant-on logic with zero boot delay （vs 5M160ZM68I5N)
- Same-BGA, four VCCIO banks for multi-voltage glue logic （vs 5M80ZM68C5N)
- Pin-compatible density upgrade path on the same PCB （vs 5M240ZM68I5N)
設計ノート
Decouple every VCCIO bank with a 0.1 uF X7R ceramic plus a 1 uF X5R bulk capacitor placed within 3 mm of the BGA balls. For the VCCINT rail add a separate 0.1 uF + 10 uF pair. The MAX V integrates an internal linear regulator that derives the 1.8 V core from VCCIO, so a clean 3.3 V VCCIO rail is required even if the user logic targets 1.8 V I/O - power-rail noise above 50 mVpp can cause JTAG programming failures.
The 68-ball MBGA uses a fine-pitch staggered ball array. Use a 4-layer PCB with a continuous GND plane directly under the package and route all signal escapes on the top layer with 4 mil trace/space. Fan-out via an inner layer with 8 mil microvias. Keep all JTAG chain traces (TMS, TCK, TDO, TDI) within 75 mm total length and add 4.7 kohm pull-ups on TMS and TDI to keep the state machine in known-good state at power-up.
Place the JTAG header (or test pads) on the same board edge as the CPLD to keep the programming cable stub under 50 mm. When using the device as a level-shifter, group the 1.8 V and 3.3 V I/O on adjacent banks and route the bank VCCIO pins with a wide 20 mil trace to bypass the internal IR drop. Avoid placing switching DC-DC converters within 10 mm of the BGA to prevent radiated EMI coupling into the analog reference inputs.
Do NOT confuse 5M80ZM68I5N with 5M80ZM64I5N - the ZM68 is 68 balls / 52 user I/Os, while the ZM64 is 64 balls / different pinout, so swapping requires a PCB redesign. Also, do NOT migrate Quartus Prime JIC files between temperature grades without recompiling, because the IO standard timing models differ across I/C/A speed grades. Finally, the device's 160-bit user flash is erasable but NOT security-locked by default - configure the security bit in the Quartus programmer before mass production.
コンプライアンス情報
RoHS compliance confirmed via distributor listings and Altera/Intel MAX V device handbook. The I5N industrial temperature grade is suitable for cabin-mounted automotive electronics but is NOT AEC-Q100 qualified - for under-hood AEC-Q100 designs, evaluate MAX V automotive variants or migrate to the MAX 10 family.
