68HC11 - 8-bit M68HC11 HCMOS Microcontroller Family | Motorola
部品番号: 68HC11 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
68HC11 概要
Background: An 8-bit microcontroller (MCU) is a single-chip processor that integrates CPU core, program memory, working RAM, and peripheral interfaces onto one semiconductor substrate. The 68HC11 belongs to the HCMOS (high-density CMOS) MCU hierarchy (microcontroller -> 8-bit MCU -> HCMOS MCU -> Motorola 6800-derived family). Its design descended from the Motorola 6800 microprocessor via the 6801, adding CMOS power economy, on-chip EEPROM, and a richer peripheral set than the 6801/6805 predecessors.
Key features include 256 to 768 bytes of on-chip RAM with standby retention, up to 20 Kbytes of ROM, EPROM, or EEPROM, an 8-channel 8-bit ADC, a synchronous and asynchronous serial peripheral interface (SPI and SCI), a programmable timer with input capture/output compare, and power-saving STOP and WAIT modes. The M68HC11E family datasheet documents selectable memory configurations of 0/256/512/768 bytes RAM, 0/12/20 Kbytes ROM, and 0/512/2048 bytes EEPROM with block-protect security.
Technically, the 68HC11 uses a HCMOS process that delivers low power and high noise immunity. The chip supports both single-chip and expanded-multiplexed bus modes selected by the MODA/MODB pins on reset. Most variants include a non-multiplexed 8-bit port, a key feature that simplifies interfacing to memory-mapped peripherals versus pure 6800 designs.
Typical applications include automotive engine control units, barcode scanners, hotel lock systems, industrial control boards, hobby SBC/single-board-computers, and legacy embedded products that require deterministic 8-bit control with on-chip EEPROM. The 68HC11 was widely adopted where cost, integrated EEPROM, and a mature toolchain outweighed the need for higher clock rates.
Design consideration: Designers choosing the 68HC11 today must weigh legacy supply continuity against newer alternatives like the 68HCS12 or 68S12. For new designs, modern 8-bit or 32-bit MCUs generally offer better price/performance. For sustaining legacy products, third-party sources such as Tekmos TK68HC11 series provide pin-compatible ROM/Flash replacements, and the DF6811 IP core from DCD offers a fully binary-compatible drop-in for FPGA/ASIC SoC integration.
This page synthesizes distributor stock, datasheet references, and cross-brand drop-in alternatives not found in a single manufacturer datasheet - giving engineers a consolidated view of lifecycle options for the M68HC11 platform.
ドロップイン代替品: 68HC11 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
MC68HC11E1CFNE3
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC68HC811E2FN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC68HC11E0FU
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TK68HC11E20FN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TK68HC11F1FN
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DF6811E
✅ ドロップイン📋 参考代替品（カタログ未掲載）
68HC11 最大定格＆電気的特性
| Architecture | 8-bit HCMOS (6801/6800-derived) |
| Family | M68HC11 (Motorola / Freescale / NXP) |
| Instruction Set | Enhanced 6800/6801 (M6800/6801 upward compatible) |
| Operating Frequency | Up to 3 MHz (at 5 V) |
| Supply Voltage (Standard) | 5 V +/- 10% |
| Supply Voltage (Low-Voltage Variant) | 3.0 V to 5.5 V |
| On-chip RAM | 0 / 256 / 512 / 768 bytes (family dependent, retained in standby) |
| On-chip ROM/EPROM | 0 / 12 / 20 Kbytes (variant dependent) |
| On-chip EEPROM | 0 / 512 / 2048 bytes (with block protect on select variants) |
| ADC | 8-channel, 8-bit (most variants) |
| Serial Interfaces | Asynchronous NRZ SCI (UART) + Synchronous SPI |
| Timer | Programmable timer with input capture / output compare / pulse accumulator |
| Operating Modes | Single-chip, Expanded, Bootstrap, Test (selected via MODA/MODB) |
| Power-Saving Modes | STOP and WAIT (data retained) |
| Common Package | PLCC-52 (FN suffix); also DIP and QFP variants |
| 動作温度 | -40C to +85C / +105C / +125C (variant dependent) |
68HC11 ピン構成
| ピン 1 | VSS — Ground reference (0 V) |
| ピン 2 | MODB/IRQ — Mode select B / Interrupt request (shared, depends on mode) |
| ピン 3 | MODA/LIR — Mode select A / Load instruction register (shared) |
| ピン 4 | RESET — Active-low reset input |
| ピン 5 | XIRQ — Non-maskable interrupt request |
| ピン 6 | IRQ — Maskable interrupt request (alternate function in some modes) |
| ピン 7 | PA7 — Port A bit 7 (digital I/O) |
| ピン 8 | PA6 — Port A bit 6 (digital I/O) |
| ピン 9 | PA5 — Port A bit 5 (digital I/O) |
| ピン 10 | PA4 — Port A bit 4 (digital I/O) |
| ピン 11 | PA3 — Port A bit 3 (digital I/O) |
| ピン 12 | PA2 — Port A bit 2 (digital I/O) |
| ピン 13 | PA1 — Port A bit 1 (digital I/O) |
| ピン 14 | PA0 — Port A bit 0 (digital I/O) |
| ピン 15 | VDD — +5 V supply (or 3.0 V for low-voltage variants) |
| ピン 16 | XTAL — Crystal oscillator output / external clock input |
| ピン 17 | EXTAL — External clock input / crystal connection |
| ピン 18 | VDDR — VDD for reset / analog reference (variant dependent) |
| ピン 19 | E — E clock output (system timing reference) |
| ピン 20 | XCLK — External clock output (variant dependent) |
| ピン 21 | PE0/RxD — Port E bit 0 / SCI receive data |
| ピン 22 | PE1/TxD — Port E bit 1 / SCI transmit data |
| ピン 23 | PE2/MISO — Port E bit 2 / SPI MISO |
| ピン 24 | PE3/MOSI — Port E bit 3 / SPI MOSI |
| ピン 25 | PE4/SCK — Port E bit 4 / SPI clock |
| ピン 26 | PE5/SS — Port E bit 5 / SPI slave select |
| ピン 27 | PE6 — Port E bit 6 (digital I/O) |
| ピン 28 | PE7 — Port E bit 7 (digital I/O) |
| ピン 29 | VRH — ADC high reference voltage |
| ピン 30 | VRL — ADC low reference voltage |
| ピン 31 | AN0/PE0 — ADC analog input 0 (channel dependent on variant) |
| ピン 32 | AN1 — ADC analog input 1 |
| ピン 33 | AN2 — ADC analog input 2 |
| ピン 34 | AN3 — ADC analog input 3 |
| ピン 35 | AN4 — ADC analog input 4 |
| ピン 36 | AN5 — ADC analog input 5 |
| ピン 37 | AN6 — ADC analog input 6 |
| ピン 38 | AN7 — ADC analog input 7 |
| ピン 39 | PD0/RxD — Port D bit 0 (alternate SCI RxD on some variants) |
| ピン 40 | PD1/TxD — Port D bit 1 (alternate SCI TxD on some variants) |
| ピン 41 | PD2/MISO — Port D bit 2 / SPI MISO |
| ピン 42 | PD3/MOSI — Port D bit 3 / SPI MOSI |
| ピン 43 | PD4/SCK — Port D bit 4 / SPI clock |
| ピン 44 | PD5/SS — Port D bit 5 / SPI slave select |
| ピン 45 | PC0/ADDR0 — Port C bit 0 / multiplexed address bit 0 (expanded mode) |
| ピン 46 | PC1/ADDR1 — Port C bit 1 / multiplexed address bit 1 |
| ピン 47 | PC2/ADDR2 — Port C bit 2 / multiplexed address bit 2 |
| ピン 48 | PC3/ADDR3 — Port C bit 3 / multiplexed address bit 3 |
| ピン 49 | PC4/ADDR4 — Port C bit 4 / multiplexed address bit 4 |
| ピン 50 | PC5/ADDR5 — Port C bit 5 / multiplexed address bit 5 |
| ピン 51 | PC6/ADDR6 — Port C bit 6 / multiplexed address bit 6 |
| ピン 52 | PC7/ADDR7/DATA — Port C bit 7 / multiplexed address bit 7 / multiplexed data bus |
主な用途
68HC11 の用途: 6 件s: Automotive Engine Control Units, Barcode Scanner Embedded Controllers, Hotel Electronic Lock Systems, Industrial PLC and Motor Control, Legacy Embedded SBCs and Education Kits, Hobby and Retro-Computing Projects.
Automotive Engine Control Units
The 68HC11 family was designed for automotive ECU applications and remains the preferred 8-bit HCMOS controller for legacy engine and body control modules. Its on-chip 2048-byte block-protected EEPROM stores fuel maps, idle-speed trim, and VIN/CAL data without an external memory chip, while the 8-channel 8-bit ADC reads manifold pressure, throttle position, coolant temperature, and battery voltage. The 68HC11's STOP and WAIT low-power modes enable crank-sensing with sub-100 uA quiescent draw, critical for battery-during-crank scenarios. Combined with its 5 V supply tolerance, the part survives the harsh automotive electrical environment and meets the -40C to +125C automotive temperature grade.
おすすめ
Barcode Scanner Embedded Controllers
The 68HC11's combination of SCI (UART), SPI, and programmable timer with input capture makes it ideal for barcode scanner decoding controllers. The SCI interfaces to a host POS terminal at 9600 to 115200 baud, while SPI drives laser-diode or CCD sensor readout. The timer input capture pins time laser-scan mirror return pulses with microsecond resolution, and the 256 to 768-byte RAM buffers decode state while the 8-bit CPU runs firmware decode loops. The 68HC11's deterministic interrupt latency (8 to 12 cycles) ensures scan timing stays within scan-beam dwell constraints.
おすすめ
Hotel Electronic Lock Systems
The 68HC11's on-chip EEPROM (512 to 2048 bytes) and low-power WAIT/STOP modes made it the standard MCU for electronic hotel lock systems. The EEPROM stores the master access list, audit trail, and battery-failure flags without a backup battery, while the UART interfaces to the key-card reader (magstripe or RFID). The 68HC11's <1 mA STOP current allows 4 x AA alkaline cells to power the lock for 3 to 5 years. The -40C to +85C operating temperature covers hotel corridor and exterior door environments, and the HCMOS noise immunity rejects RF interference from card readers and electric strikes.
おすすめ
Industrial PLC and Motor Control
The 68HC11's 16-bit timer with pulse accumulator, PWM channels, and 8-channel ADC supports small PLC and motor-control applications. The programmable timer generates fixed-frequency PWM for DC motor speed control, while the ADC reads current shunt amplifiers and thermistor inputs. The 68HC11's HCMOS noise immunity and 5 V tolerance survive industrial factory-floor EMI. With 20 Kbytes of ROM it holds ladder-logic interpreter and PID control firmware. The expanded bus mode allows external program memory for PLCs that need >20K logic instructions.
おすすめ
Legacy Embedded SBCs and Education Kits
The 68HC11 is the canonical MCU for educational single-board computers (SBCs) and legacy embedded training kits such as the Motorola EVB and Freescale M68EVB11. Its simple memory map, well-documented serial bootloader, and mature 6800/6801 instruction set make it ideal for teaching low-level embedded programming. SBC manufacturers continue sourcing 68HC11 through Rochester Electronics and Tekmos for ongoing product support. Combined with the 68HC11's debug-friendly Bootstrap mode, this educational role has persisted for 40+ years.
おすすめ
Hobby and Retro-Computing Projects
The 68HC11 powers a thriving retro-computing hobby community, including the QCard controller, HC11 SBC boards, and DIY calculator/computer projects. Its QFP-64 and DIP packages remain accessible to hobbyists soldering by hand, and its 6801/6800 instruction set is well documented in textbooks and online tutorials. Third-party Flash replacements like Tekmos TK68HC11 make hobby builds easier to program and re-flash. Combined with open-source assemblers, BASIC interpreters, and FORTH firmware ports, the 68HC11 continues to introduce new engineers to bare-metal 8-bit programming.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 68HC11 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MC68HC11E1CFNE3 | MC68HC811E2FN | MC68HC11E0FU | TK68HC11E20FN | TK68HC11F1FN | DF6811E |
|---|---|---|---|---|---|---|---|
| Package | PLCC-52 (FN) family | PLCC-52 (FN) | PLCC-52 (FN) | QFP-64 (FU) | PLCC-52 (FN) | PLCC-52 (FN) | IP Core (FPGA/ASIC) |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Tekmos | Tekmos | DCD |
| Architecture | 8-bit HCMOS 6801/6800-derived | 8-bit HCMOS 6801-derived | 8-bit HCMOS 6801-derived | 8-bit HCMOS 6801-derived | 8-bit HCMOS 6801-derived | 8-bit HCMOS 6801-derived | 8-bit IP core, binary-compatible |
| On-chip RAM | 256 / 512 / 768 bytes (variant dependent) | 512 bytes | 256 bytes | 512 bytes (ROMless) | 512 bytes | 1024 bytes | Configurable (IP) |
| On-chip ROM/Flash | 0 / 12 / 20 Kbytes ROM | 0 (ROMless) | 0 (ROMless + 2KB EEPROM) | 0 (ROMless) | 20 Kbytes Flash | Flash (F-series capacity) | Configurable (IP) |
| On-chip EEPROM | 0 / 512 / 2048 bytes | 512 bytes | 2048 bytes (with block protect) | 512 bytes | Configurable (Flash, no separate EEPROM) | Configurable | Configurable (IP) |
| Max Clock Frequency | 3 MHz @ 5 V | 3 MHz @ 5 V | 3 MHz @ 5 V | 3 MHz @ 5 V | 3 MHz @ 5 V | 3 MHz @ 5 V | Configurable, up to 50 MHz in FPGA |
| Supply Voltage | 5 V standard, 3.0 to 5.5 V low-voltage variant | 5 V / 3.0-5.5 V | 5 V | 5 V | 5 V / 3.0-5.5 V | 5 V / 3.0-5.5 V | IP core, FPGA supply |
| Manufacturer Status | NXP (N/RND for new designs; selected variants active) | NXP active | NXP active | NXP active (Rochester stocked) | Tekmos (third-party replacement, ongoing) | Tekmos (third-party replacement) | DCD (FPGA/ASIC IP core) |
| Price (USD, qty-1 reference) | USD 18.50 (family average) | USD 19-22 | USD 22-28 | USD 17-21 | Quote-based | Quote-based | License-based (IP core) |
主な差別化要因
- Authentic NXP 68HC11E-series with doubled RAM and continued manufacturer support （vs MC68HC11A1 (legacy NXP device))
- Larger 2 KB EEPROM with selectable base address for data storage （vs MC68HC11E1CFNE3 (512 bytes EEPROM))
- ROMless variant for QFP-64 footprint migration without firmware rewrite （vs PLCC-52 ROMless variant)
- Third-party Flash replacement enables field firmware updates vs masked ROM （vs Original Motorola/NXP masked-ROM 68HC11E20)
設計ノート
Do not assume the 68HC11 is a 5 V-only part. Low-voltage variants (3.0 to 5.5 V) are documented in the M68HC11E datasheet and require verifying the specific MPN suffix before PCB assembly. Power-rail decoupling must use a 100 nF ceramic plus 10 uF tantalum or ceramic bulk capacitor within 5 mm of the VDD/VSS pins. Without proper decoupling the HCMOS internal logic is susceptible to voltage transients that cause erratic resets.
PLCC-52 sockets are recommended over direct soldering for prototyping because PLCC packages are leadless and difficult to rework. The original PLCC-52 footprint is now considered obsolete for new designs; if laying out a new board, consider Tekmos LQFP-52 (PB package) which fits within the PLCC-52 land pattern and offers Flash reprogrammability. Place the external crystal within 5 mm of XTAL/EXTAL pins with guard traces to reduce noise injection.
The 68HC11 E clock output (E pin) generates a 50% duty cycle bus clock equal to one-fourth of the crystal frequency. In expanded mode this clock drives external memory and peripherals, so the E trace must be length-matched to the address/data bus to avoid setup/hold violations at 3 MHz. Place a 100 ohm series termination resistor at the E clock driver if the trace length exceeds 50 mm. Use Schmitt-trigger buffers on reset and IRQ lines to prevent false triggers from EMI.
At 3 MHz and 5 V supply, the 68HC11's typical quiescent current is 5 to 15 mA in RUN mode and <100 uA in STOP mode. Estimated: total power dissipation = Vdd * Idd = 5 V * 10 mA = 50 mW, well below thermal limits. However, at industrial temperature grade (-40C to +85C) the oscillator startup time after STOP wake can exceed 100 ms; verify the crystal startup spec at the lowest operating temperature to ensure reliable wake-up behavior.
Use the STOP and WAIT instructions aggressively for battery-powered designs. STOP halts the CPU and on-chip peripherals, retaining RAM and register contents with <100 uA draw; WAIT halts only the CPU while peripherals run, drawing 2 to 5 mA. Wake-up from STOP requires the IRQ, XIRQ, or RESET pin. For bootloader development, leverage the Bootstrap mode (set by holding MODA high and MODB low on reset) to load user code via SCI from a host PC.
コンプライアンス情報
Specific RoHS/REACH/AEC-Q100 compliance depends on the exact 68HC11 sub-variant MPN and production year. The legacy Motorola 68HC11 family predates RoHS (2006); many original parts are non-RoHS, while NXP-revised and Tekmos replacement variants may be RoHS compliant. Verify the specific MPN's compliance certificate before use in automotive or EU-market products.
