AD7770ACPZ - 8-Ch 24-Bit 32kSPS Simultaneous-Sampling Sigma-Delta ADC | ADI
部品番号: AD7770ACPZ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.95 | $259.50 |
| 100 | $23.1 | $2,310.00 |
| 500 | $20.85 | $10,425.00 |
| 1,000 | $18.6 | $18,600.00 |
AD7770ACPZ 概要
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, sitting in the signal chain hierarchy between sensors/front-ends and digital processors or MCUs. The AD7770 belongs to the precision sigma-delta ADC sub-category, which trades conversion speed for very high effective resolution by oversampling and digital filtering; within that sub-category it is a multi-channel simultaneous-sampling part, meaning all eight cores convert at the same instant, preserving phase information critical for three-phase power, vibration, and biomedical instrumentation.
Key differentiating features include a sample rate converter (SRC) enabling coherent sampling with resolution up to 15.2×10⁻⁶ SPS, a low-latency sinc³ filter path, on-chip per-channel PGAs, and very low input current that allows direct connection to current-sense transformers, shunt resistors, and piezoelectric sensors without loading effects. These features minimize external signal-conditioning components.
Technically, the AD7770 integrates eight independent sigma-delta modulator cores plus a shared digital filter/decimation engine. The SRC allows the output data rate to be programmed to any value between the modulator rate and very low rates without losing integer decimation ratios, simplifying synchronization to mains frequency (50/60 Hz). On-chip calibration and temperature-compensation registers correct gain and offset drift.
Typical applications include three-phase power-quality and energy-metering front-ends, vibration and modal analysis, multiphase motor control, industrial process-control PLC analog modules, and multi-channel data-acquisition systems. Direct sensor interface with low input current suits shunt-based current sensing and Rogowski-coil current transducers.
Design consideration: input common-mode voltage must be within the PGA input range and the reference voltage (typically an external ADR45xx series) determines absolute accuracy; add anti-aliasing RC networks at each input pin when broadband noise sources are present.
This page synthesizes distributor pricing, drop-in same-brand and cross-brand alternatives, application references and design notes beyond the datasheet to give a single engineering-ready view of the AD7770ACPZ.
ドロップイン代替品: AD7770ACPZ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: AD7770ACPZ （同一形状・フットプリント） — 相違点: Interface, Operating Temperature Range, Package, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
AD7771BCPZ
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$25.3 / 個
データシートを見る →AD7779ACPZ
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AD7770ACPZ-RL
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7770ACPZ 最大定格＆電気的特性
| 分解能 | 24-bit |
| Number of Channels | 8 |
| Sampling Architecture | Sigma-Delta, simultaneous sampling |
| Maximum Output Data Rate (per channel) | 32 kSPS |
| Input Type | Single-ended or true differential |
| Programmable Gain (PGA) | 1, 2, 4, 8 |
| Differential DC Input Current | ±4 nA |
| Single-Ended DC Input Current | ±8 nA |
| Sample Rate Converter (SRC) Resolution | Up to 15.2 × 10⁻⁶ SPS |
| Digital Filter | Low-latency sinc3, plus decimation FIR options |
| パッケージ | 64-LFCSP (9x9 mm) |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40C to +125C |
| インターフェース | SPI / QSPI / MICROWIRE / DSP-compatible serial |
| RoHS ステータス | Compliant |
AD7770ACPZ ピン構成
| ピン 1 | AIN0+ — Channel 0 positive analog input |
| ピン 2 | AIN0- — Channel 0 negative analog input |
| ピン 3 | AIN1+ — Channel 1 positive analog input |
| ピン 4 | AIN1- — Channel 1 negative analog input |
| ピン 5 | AIN2+ — Channel 2 positive analog input |
| ピン 6 | AIN2- — Channel 2 negative analog input |
| ピン 7 | AIN3+ — Channel 3 positive analog input |
| ピン 8 | AIN3- — Channel 3 negative analog input |
| ピン 9 | AGND — Analog ground |
| ピン 10 | REFIN+ — Positive reference input |
| ピン 11 | REFIN- — Negative reference input |
| ピン 12 | REGCAPA — Regulator capacitor A |
| ピン 13 | REGCAPB — Regulator capacitor B |
| ピン 14 | AVDD — Analog supply voltage |
| ピン 15 | AVSS — Analog ground |
| ピン 16 | IOVDD — Digital I/O supply |
| ピン 17 | IOGND — Digital I/O ground |
| ピン 18 | CS — Chip select (active low) |
| ピン 19 | SCLK — Serial clock |
| ピン 20 | MOSI — Master out / slave in data |
| ピン 21 | MISO — Master in / slave out data |
| ピン 22 | DRDY — Data ready output |
| ピン 23 | SYNC_IN — Sync input for multi-device clock |
| ピン 24 | SYNC_OUT — Sync output for multi-device clock |
| ピン 25 | MCLK — Master clock input |
| ピン 26 | CLKIO — Clock I/O |
| ピン 27 | RESET — Reset input (active low) |
| ピン 28 | GPIO0 — General-purpose I/O 0 |
| ピン 29 | GPIO1 — General-purpose I/O 1 |
| ピン 30 | GPIO2 — General-purpose I/O 2 |
| ピン 31 | GPIO3 — General-purpose I/O 3 |
| ピン 32 | NC — Not connected |
| ピン 33 | AIN4+ — Channel 4 positive analog input |
| ピン 34 | AIN4- — Channel 4 negative analog input |
| ピン 35 | AIN5+ — Channel 5 positive analog input |
| ピン 36 | AIN5- — Channel 5 negative analog input |
| ピン 37 | AIN6+ — Channel 6 positive analog input |
| ピン 38 | AIN6- — Channel 6 negative analog input |
| ピン 39 | AIN7+ — Channel 7 positive analog input |
| ピン 40 | AIN7- — Channel 7 negative analog input |
| ピン 41 | AGND — Analog ground |
| ピン 42 | TEMP — Temperature sensor output |
| ピン 43 | REFOUT — Internal reference output |
| ピン 44 | REFIN2+ — Reference input 2 positive |
| ピン 45 | REFIN2- — Reference input 2 negative |
| ピン 46 | AVDD2 — Analog supply 2 |
| ピン 47 | AVSS2 — Analog ground 2 |
| ピン 48 | NC — Not connected |
| ピン 49 | NC — Not connected |
| ピン 50 | NC — Not connected |
| ピン 51 | NC — Not connected |
| ピン 52 | NC — Not connected |
| ピン 53 | NC — Not connected |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | NC — Not connected |
| ピン 57 | NC — Not connected |
| ピン 58 | NC — Not connected |
| ピン 59 | NC — Not connected |
| ピン 60 | NC — Not connected |
| ピン 61 | NC — Not connected |
| ピン 62 | NC — Not connected |
| ピン 63 | NC — Not connected |
| ピン 64 | NC — Not connected |
主な用途
AD7770ACPZ の用途: 6 件s: Three-Phase Power Quality & Energy Metering, Industrial Process Control & PLC Analog Modules, Vibration & Modal Analysis Systems, Multiphase Motor Control Drive Feedback, Medical Multi-Channel Patient Monitoring, Multi-Channel Data Acquisition Systems.
Three-Phase Power Quality & Energy Metering
The AD7770ACPZ's 8 simultaneous-sampling 24-bit channels allow direct connection of three voltage dividers and three current transformers per phase plus neutral, while the sample rate converter locks precisely to 50/60 Hz mains for coherent sampling and IEC 62053-22x class-0.2 accuracy. Each PGA gain of 1/2/4/8 adapts to current-sense shunt ranges from milliamps to hundreds of amps without external conditioning, and ±4 nA input current minimizes burden on CTs.
おすすめ
Industrial Process Control & PLC Analog Modules
Eight simultaneously-sampled 24-bit channels let a single AD7770ACPZ replace eight discrete ADC channels in PLC analog input modules, dramatically reducing board area while maintaining channel-to-channel phase coherence. The integrated PGA accepts 4-20 mA, 0-10 V and thermocouple inputs after external scaling, and the SPI/QSPI interface connects to most host MCUs or industrial processors. Low input current of ±4 nA avoids loading high-impedance sensor networks.
おすすめ
Vibration & Modal Analysis Systems
Up to 32 kSPS per channel on 8 channels gives the AD7770ACPZ enough oversampling ratio for vibration and modal analysis on multi-axis accelerometers and IEPE microphones. Simultaneous sampling captures phase relationships between sensor axes, essential for FFT-based modal extraction. The sinc3 low-latency path reduces group delay so closed-loop modal control loops remain stable.
おすすめ
Multiphase Motor Control Drive Feedback
Three-phase motor drives with current and voltage feedback on each phase benefit from the AD7770ACPZ's simultaneous sampling - all phase measurements are taken at the same instant for accurate field-oriented control (FOC) calculations. PGA gains handle shunt-based current sensing at various current levels and the SRC allows the ADC to lock to PWM frequency for sub-cycle oversampling. Low input current of ±4 nA suits shunt direct interface.
おすすめ
Medical Multi-Channel Patient Monitoring
Bio-signal acquisition for ECG, EEG and EMG arrays needs simultaneous sampling of multiple electrode channels - the AD7770ACPZ's 8 channels, low input current of ±4 nA, and 24-bit resolution make it ideal for active-electrode arrays. The PGA handles skin-electrode impedance variations and the integrated decimation filter reduces host processing load for portable patient monitors.
おすすめ
Multi-Channel Data Acquisition Systems
Compact multi-channel data-acquisition systems for laboratory, ATE and structural monitoring can use the AD7770ACPZ to digitize 8 sensor channels with simultaneous phase coherence in a single 9x9 mm LFCSP. The SPI interface supports daisy-chaining of multiple AD7770 chips for 16-, 24- or 32-channel systems. Low input current allows direct connection to high-impedance strain gauges, RTDs and piezoelectric sensors.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD7770ACPZ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD7771BCPZ | AD7779ACPZ | AD7770ACPZ-RL |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-LFCSP (9x9) | 64-LFCSP (9x9) - same | 64-LFCSP (9x9) - same | 64-LFCSP (9x9) - same |
| Number of Channels | 8 | 8 | 8 | 8 |
| Resolution | 24-bit | 24-bit | 24-bit | 24-bit |
| Maximum Output Data Rate | 32 kSPS per channel | 32 kSPS per channel | 32 kSPS per channel | 32 kSPS per channel |
| PGA Gains | 1, 2, 4, 8 | 1, 2, 4, 8 | 1, 2, 4, 8 | 1, 2, 4, 8 |
| Differential DC Input Current | ±4 nA | ±4 nA | ±4 nA | ±4 nA |
| Sample Rate Converter | Yes (15.2×10⁻⁶ SPS resolution) | Yes | Yes | Yes |
| Primary Optimization | Low-frequency DC (strain gauge, temperature, polyphase metering) |
主な差別化要因
- 8 channels with simultaneous sampling in single 64-LFCSP （vs Discrete 8xAD7173 design)
- Sample Rate Converter for coherent mains sampling （vs AD7768 (no SRC))
- ±4 nA ultra-low DC input current for direct sensor interface （vs ADS131A08 (TI) input bias current)
設計ノート
The 64-LFCSP exposed thermal pad MUST be soldered to a continuous ground plane on the PCB for both thermal dissipation and electrical reference. Use 9x9 mm land pads with at least 9 thermal vias (0.3 mm drill) connecting the pad to inner ground layers. Each input pair (AINx+, AINx-) should be routed as a differential pair with matched length and 50 ohm characteristic impedance, kept away from digital traces. Place the reference decoupling capacitors (10 µF + 100 nF X7R) within 5 mm of REFIN± pins to avoid reference noise coupling into the conversion result.
Use separate analog (AVDD) and digital (IOVDD) supply rails. AVDD should be derived from a low-noise LDO (e.g. ADP7118) with pi-filter (10 µF + ferrite bead + 10 µF) to reject switching converter ripple. IOVDD typically matches the host MCU logic level (3.3 V or 1.8 V). Keep REGCAPA and REGCAPB capacitors as close as possible to their pins - these internal LDO regulators require 1 µF X7R. Estimated: total AD7770ACPZ quiescent current draw is approximately 30-50 mA across all supplies at full ODR per the datasheet power specifications.
Place anti-aliasing RC filters on each analog input as close to the IC as possible. A first-order RC with 1 kohm and 100 pF gives a 1.6 MHz -3 dB cutoff, sufficient for 32 kSPS maximum ODR with the sigma-delta oversampling providing its own alias rejection. Keep input traces short and guarded with ground. The internal PGA's common-mode input range is approximately AVDD/2 ±Vref/2; ensure the input signal stays within this window. The sample rate converter (SRC) allows the output data rate to be programmed to any sub-multiple of the MCLK for perfect mains synchronization - set ODR to 60/50 Hz × integer for clean line-cycle averaging.
Do not leave any analog input floating when its channel is enabled - floating inputs cause excessive modulator current and degrade SNR. Tie unused channels to mid-supply through 1 kohm resistors. Avoid using the internal REFOUT to drive external circuitry beyond 100 µA load - use a dedicated ADR45xx external reference for high-accuracy applications. The DRDY signal MUST be monitored in the host firmware; reading data without checking DRDY causes conversion-result register overrun. Finally, never write to reserved registers (per the datasheet register map) - this can put the device in an unrecoverable state requiring a hardware reset.
コンプライアンス情報
RoHS compliant per Analog Devices product page. AEC-Q100 grade not specified for this part - not targeted at automotive safety applications. Lead-free packaging confirmed.
