AD9680 - 14-Bit 1.25 GSPS Dual ADC | Analog Devices
部品番号: AD9680 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $401.64 | $401.64 |
| 10 | $380 | $3,800.00 |
| 100 | $350 | $35,000.00 |
| 500 | $320 | $160,000.00 |
| 1,000 | $300 | $300,000.00 |
AD9680 概要
An analog-to-digital converter (ADC) is a device that converts continuous analog signals into discrete digital numbers. The AD9680 is a high-speed, dual-channel ADC that samples at rates up to 1.25 GSPS, making it suitable for wideband signals. It uses a pipelined architecture to achieve high throughput with low latency. The device includes a JESD204B serial interface for high-speed data transfer to FPGAs or ASICs, reducing the number of I/O pins required.
Key features include 14-bit resolution, dual-channel operation, and sample rates up to 1.25 GSPS. The device offers excellent dynamic performance with high SFDR and SNR, making it suitable for demanding applications. It also includes a programmable gain amplifier (PGA) and digital down-conversion (DDC) options for flexible signal processing. The JESD204B interface supports lane rates up to 15 Gbps, enabling high-speed data transfer.
The AD9680 uses a pipelined ADC architecture with digital error correction, achieving high linearity and low noise. The on-chip buffer eliminates the need for external drivers, simplifying the front-end design. The device also includes a sample-and-hold circuit that ensures accurate sampling of high-frequency signals. The LFCSP package provides excellent thermal performance and is suitable for space-constrained designs.
Typical applications include radar systems, software-defined radio, test and measurement equipment, and communications infrastructure. The AD9680's high sample rate and resolution make it ideal for capturing wideband signals with high fidelity. Its dual-channel configuration enables I/Q demodulation in quadrature receivers, reducing system complexity.
When designing with the AD9680, ensure proper power supply decoupling and a clean clock source to achieve optimal performance. The JESD204B interface requires careful PCB layout to maintain signal integrity at high lane rates. Refer to the datasheet for recommended layout guidelines and configuration register settings.
ドロップイン代替品: AD9680 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: AD9680 （同一形状・フットプリント） — 相違点: Package, Supply Voltage, Resolution, Number of Inputs, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
AD9234
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD6674
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
GMS011
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9680BCPZ-1250
✅ ドロップイン✓ 在庫あり
$840 / 個
データシートを見る →AD9680BCPZ-1000
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
価格はお問い合わせください
データシートを見る →AD9680 最大定格＆電気的特性
| 分解能 | 14 bits |
| Number of Channels | 2 |
| サンプリングレート | 1.25 GSPS (max) |
| Input Type | Differential |
| インターフェース | JESD204B |
| 電源電圧 | 1.2 V/2.5 V |
| パッケージ | 64-LFCSP (9x9 mm) |
| 動作温度 | -40C to +85C |
| SFDR | 85 dBFS (typ) |
| SNR | 65.3 dBFS (typ) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
AD9680 ピン構成
| ピン 1 | VIN+ — Positive analog input |
| ピン 2 | VIN- — Negative analog input |
| ピン 3 | VCM — Common-mode voltage output |
| ピン 4 | CLK+ — Positive clock input |
| ピン 5 | CLK- — Negative clock input |
| ピン 6 | AVDD — Analog power supply |
| ピン 7 | DVDD — Digital power supply |
| ピン 8 | GND — Ground |
| ピン 9 | SDO — Serial data output |
| ピン 10 | SDIO — Serial data I/O |
| ピン 11 | SCLK — Serial clock |
| ピン 12 | CSB — Chip select (active low) |
主な用途
AD9680 の用途: 6 件s: Radar Systems, Software-Defined Radio, Test and Measurement, Communications Infrastructure, Medical Imaging, Electronic Warfare.
Radar Systems
The AD9680's 14-bit resolution and 1.25 GSPS sampling rate enable high-fidelity capture of wideband radar returns. Its dual-channel architecture supports I/Q demodulation, and the JESD204B interface simplifies data transfer to FPGAs for real-time processing. The high SFDR of 85 dBFS ensures weak target detection in cluttered environments.
おすすめ
Software-Defined Radio
In SDR applications, the AD9680 digitizes wideband RF signals directly, eliminating multiple downconversion stages. Its high sample rate and 14-bit resolution provide excellent dynamic range for detecting weak signals alongside strong interferers. The JESD204B interface reduces pin count and simplifies FPGA integration, making it ideal for multi-channel SDR platforms.
おすすめ
Test and Measurement
The AD9680 is well-suited for oscilloscopes and spectrum analyzers requiring high-speed, high-resolution digitization. Its dual channels enable simultaneous acquisition of I/Q signals, and the on-chip buffer simplifies front-end design. The device's low power consumption and small LFCSP package make it ideal for portable test equipment.
おすすめ
Communications Infrastructure
For 5G and other communications systems, the AD9680 provides high linearity and wide bandwidth for digitizing multiple carriers. Its 14-bit resolution ensures low error vector magnitude (EVM) in QAM modulation schemes. The JESD204B interface supports high lane rates, enabling efficient data transfer to baseband processors.
おすすめ
Medical Imaging
In ultrasound and MRI systems, the AD9680's high sample rate and resolution enable precise digitization of analog signals. Its low noise performance (SNR 65.3 dBFS) is critical for image quality. The dual-channel configuration supports phased-array transducers, and the small package allows for compact probe designs.
おすすめ
Electronic Warfare
The AD9680 is used in electronic warfare systems for wideband signal interception and analysis. Its high instantaneous bandwidth and 14-bit resolution allow detection of low-probability-of-intercept signals. The dual-channel architecture supports direction-finding applications, and the JESD204B interface enables rapid data transfer to processing units.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD9680 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD9234 | AD6674 | GMS011 |
|---|---|---|---|---|
| Package | 64-LFCSP (9x9 mm) | 64-LFCSP (9x9 mm) | 64-LFCSP (9x9 mm) | 64-LFCSP (9x9 mm) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Superb Automation |
| Resolution | 14 bits | 12 bits | 14 bits | 14 bits |
| Max Sampling Rate | 1.25 GSPS | 1 GSPS | 1 GSPS | 1 GSPS |
| Interface | JESD204B | JESD204B | JESD204B | JESD204B |
| Supply Voltage | 1.2 V/2.5 V | 1.2 V/2.5 V | 1.2 V/2.5 V | 1.2 V/2.5 V |
主な差別化要因
- Higher resolution than AD9234 （vs AD9234)
- Pin-to-pin compatible with GMS011 （vs GMS011)
- Higher sampling rate than AD6674 （vs AD6674)
設計ノート
The AD9680 requires clean power supplies for optimal performance. Use low-dropout regulators (LDOs) for AVDD and DVDD, and place decoupling capacitors (0.1 uF and 10 uF) close to each power pin. A ferrite bead can be used to isolate analog and digital supplies. Refer to the datasheet for recommended power supply sequencing.
For the JESD204B interface, maintain controlled impedance (100 ohm differential) for the high-speed lanes. Keep trace lengths matched and minimize vias. Use ground planes under the ADC and avoid routing digital signals near analog inputs. Follow the layout guidelines in the datasheet to achieve specified SFDR and SNR.
The AD9680's power dissipation is [DATA_NEEDED], but the 64-LFCSP package has an exposed pad for thermal relief. Solder the pad to a large copper area on the PCB to improve heat dissipation. For high ambient temperatures, consider adding thermal vias. Ensure the junction temperature stays within the operating range.
コンプライアンス情報
RoHS compliant per Analog Devices product page. Other compliance data not specified in provided sources.
