ADC0804S040TS/C1:1 - 8-bit 40 MSPS ADC, 28-SSOP | NXP
部品番号: ADC0804S040TS/C1:1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $5.8 | $5.80 |
| 10 | $5.2 | $52.00 |
| 100 | $4.6 | $460.00 |
| 500 | $4.05 | $2,025.00 |
| 1,000 | $3.5 | $3,500.00 |
ADC0804S040TS/C1:1 概要
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog input signals into discrete digital codes, acting as the bridge between the analog physical world (sensors, video, RF) and digital processing (FPGAs, microcontrollers, DSPs). The 8-bit resolution means the input range is divided into 256 discrete quantization levels, giving a theoretical SNR of approximately 49.9 dB (6.02 dB/bit + 1.76 dB). In the data-acquisition signal chain hierarchy, ADCs sit between analog front-end conditioning (amplifiers, filters) and the digital domain, and they are categorized as data converters within the data acquisition and converter IC family.
Key specifications include a single analog input channel, parallel 8-bit TTL/CMOS-compatible output, 40 MSPS maximum sampling rate, 5V single-supply operation, low power consumption, and TTL/CMOS-compatible digital I/O. The device uses a flash or half-flash (pipelined) architecture to achieve the 40 MSPS conversion rate with low latency suitable for real-time video processing. The 28-SSOP package with gull-wing leads is rated MSL1 at 260C peak reflow and supports commercial-grade temperature operation.
Typical applications include professional video digitizers (SD/ED broadcast equipment), intermediate-frequency (IF) signal digitization, digital oscilloscope front-ends, CCD image sensor read-out, medical imaging, set-top box video capture, and high-speed instrumentation. The 40 MSPS rate makes it well-suited for digitizing standard-definition video at full bandwidth and undersampled IF signals in software-defined radio designs.
Designers should note that proper analog input drive with a wide-bandwidth op-amp (such as an ADA4862 or LMH6702) and careful PCB layout with separate analog and digital ground planes are essential to achieve the rated ENOB. The single 5V supply and parallel interface simplify integration but require careful bus impedance matching when interfacing directly to an FPGA.
This page synthesizes distributor pricing, drop-in SSOP-28 alternatives from the same ADC0806030/040/050 family and cross-brand sources, plus practical design notes not found in the manufacturer datasheet alone, helping engineers select and apply this 40 MSPS video-grade ADC quickly.
ドロップイン代替品: ADC0804S040TS/C1:1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC0804S040TS/C1:1 （同一形状・フットプリント） — 相違点: Architecture, Output Interface, Package, Resolution, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ADC0803S030TS/C1:1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADC0805S050TS/C1:1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADC0801S040TS/C1:1
✅ ドロップイン✓ 在庫あり
$1.95 / 個
データシートを見る →ADC0804S040TS/C1
✅ ドロップイン✓ 在庫あり
$4.05 / 個
データシートを見る →ADC0804S030TS/C1:1
✅ ドロップイン✓ 在庫あり
$4.65 / 個
データシートを見る →ADC0804S040TS/C1:1 最大定格＆電気的特性
| 分解能 | 8 bit |
| Number of Channels | 1 |
| サンプリングレート | 40 MSPS (max) |
| Input Type | Single-ended |
| Output Interface | Parallel, TTL/CMOS compatible |
| Output Bit Code | Offset Binary |
| 電源電圧 | 5 V (single supply) |
| Architecture | Flash / high-speed pipelined |
| 動作温度 | 0C to +70C (commercial) |
| パッケージ | 28-SSOP (SOT341-1, MO-150), 5.30 mm body |
| 実装タイプ | Surface Mount |
| Terminal Form | Gull Wing |
| Terminal Finish | Matte Tin (Sn) |
| Peak Reflow Temperature | 260C (JEDEC J-STD-020) |
| RoHS ステータス | Compliant (e3 finish) |
| Screening Level | Commercial |
| ピン数 | 28 |
ADC0804S040TS/C1:1 ピン構成
| ピン 1 | VDDA — Analog supply voltage (5V) |
| ピン 2 | VIN — Analog input |
| ピン 3 | AGND — Analog ground |
| ピン 4 | VRT — Top reference voltage |
| ピン 5 | VRB — Bottom reference voltage |
| ピン 6 | REFOUT — Internal reference output |
| ピン 7 | REFIN — Reference input |
| ピン 8 | CLK — Conversion clock input |
| ピン 9 | DGND — Digital ground |
| ピン 10 | VDDD — Digital supply voltage (5V) |
| ピン 11 | OE — Output enable (active low) |
| ピン 12 | D0 — Data output bit 0 (LSB) |
| ピン 13 | D1 — Data output bit 1 |
| ピン 14 | D2 — Data output bit 2 |
| ピン 15 | D3 — Data output bit 3 |
| ピン 16 | D4 — Data output bit 4 |
| ピン 17 | D5 — Data output bit 5 |
| ピン 18 | D6 — Data output bit 6 |
| ピン 19 | D7 — Data output bit 7 (MSB) |
| ピン 20 | NC — Not connected |
| ピン 21 | NC — Not connected |
| ピン 22 | NC — Not connected |
| ピン 23 | NC — Not connected |
| ピン 24 | NC — Not connected |
| ピン 25 | NC — Not connected |
| ピン 26 | NC — Not connected |
| ピン 27 | NC — Not connected |
| ピン 28 | NC — Not connected |
主な用途
ADC0804S040TS/C1:1 の用途: 7 件s: Professional Video Digitization, IF Signal Undersampling (SDR Front-End), Digital Oscilloscope Acquisition Channel, CCD Image Sensor Read-Out, Medical Imaging Front-End (Ultrasound/Endoscope), Set-Top Box / Video Capture Card, High-Speed Data Acquisition Card (PCI/USB).
Professional Video Digitization
The ADC0804S040TS/C1:1's 40 MSPS sampling rate and 8-bit resolution are well-matched to standard-definition digital video (CCIR-601/SMPTE 259M) where the 27 MHz pixel clock plus headroom for color subcarrier sampling demand 35-40 MSPS. The parallel 8-bit TTL output simplifies interfacing to an FPGA-based video pipeline (such as a Xilinx XC6SLX16 or Altera Cyclone), avoiding serializer overhead at these data rates. In an SDI capture card or broadcast monitor, the ADC drives the digital video processor with adequate ENOB for luminance/chroma separation while keeping the BOM low. The 5V single supply and SSOP-28 footprint ease integration into compact video modules.
おすすめ
IF Signal Undersampling (SDR Front-End)
At 40 MSPS with 8-bit resolution, the ADC0804S040TS/C1:1 can undersample intermediate-frequency (IF) signals up to ~20 MHz, applying the Nyquist criterion to band-pass signals rather than baseband. This is ideal for software-defined radio receivers where the 21.4 MHz IF is digitized directly without a final analog mixer. The TTL-compatible clock input accepts a low-level sine wave from a TCXO or PLL synthesizer, and the 8-bit parallel output feeds an FPGA FFT processor for demodulation. ADC0806030/040/050 family parts have been deployed in commercial SDR and spectrum-analyzer front-ends because of this bandwidth/cost trade-off.
おすすめ
Digital Oscilloscope Acquisition Channel
Digital storage oscilloscopes (DSOs) in the 50-100 MHz bandwidth class use 8-bit ADCs at 100-500 MSPS, but for entry-level 20-40 MHz bandwidth scopes the ADC0804S040TS/C1:1 provides sufficient real-time sampling. At 40 MSPS, single-shot bandwidth is limited to ~6 MHz by Nyquist, but equivalent-time sampling modes extend the effective bandwidth significantly. The parallel 8-bit output interfaces directly to an FPGA acquisition memory buffer; the 5V single supply and commercial 0C-70C temperature range fit typical bench-instrument thermal budgets. Lower-cost scope manufacturers have used this 40 MSPS ADC for educational and hobbyist oscilloscope platforms.
おすすめ
CCD Image Sensor Read-Out
Scientific and industrial CCD line-scan cameras generate pixel rates from 10-50 MHz depending on resolution and line time. A 40 MSPS 8-bit ADC like the ADC0804S040TS/C1:1 digitizes each CCD output pixel with 256 grayscale levels, providing sufficient dynamic range for monochrome machine-vision inspection of documents, web materials, and printed-circuit boards. The TTL/CMOS-compatible parallel output interfaces to a microcontroller or FPGA that performs dark-current subtraction, gain correction, and data packing. The SSOP-28 footprint is compact enough for line-scan camera heads where board space is at a premium.
おすすめ
Medical Imaging Front-End (Ultrasound/Endoscope)
Diagnostic ultrasound receivers and digital endoscope signal chains digitize pre-processed analog video at rates up to 40 MSPS. The ADC0804S040TS/C1:1 fits within this 8-bit 30-50 MSPS window for video-grade processing, where the analog front-end (TGC amplifier and demodulator) provides the dynamic range. The single 5V supply simplifies isolated medical power designs, and the commercial 0C-70C temperature range matches the controlled thermal environment of cart-based equipment. The 28-SSOP footprint fits compact probe-electronics PCBs.
おすすめ
Set-Top Box / Video Capture Card
Set-top boxes, DVR capture cards, and HDMI-to-USB capture dongles that accept composite or component analog video use 8-bit ADCs at 27-40 MSPS to digitize NTSC/PAL/SECAM baseband video. The ADC0804S040TS/C1:1 handles the full CCIR-601 pixel rate with margin, and its parallel output drives an MPEG/H.264 encoder chip or an FPGA video pipeline. Consumer volumes benefit from the SSOP-28 footprint that reflows easily on standard SMT lines. Combined with a video op-amp (e.g. AD8001) for input clamping and anti-alias filtering, this ADC is a classic consumer-video front-end building block.
おすすめ
High-Speed Data Acquisition Card (PCI/USB)
Multi-channel data-acquisition (DAQ) cards for PC instrumentation often combine several 8-bit ADCs at 30-50 MSPS to reach aggregate sampling rates of 100-200 MSPS across parallel channels. The ADC0804S040TS/C1:1 serves as a single channel in such cards, with each ADC phase-shifted by 1/N of the sample interval. The parallel output supports DMA transfer into a Xilinx Kintex Ultrascale FPGA that buffers and forwards to the host bus (PCIe or USB 3.0). This time-interleaving pattern is documented in NXP application notes for the ADC0806030/040/050 family.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC0804S040TS/C1:1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC0803S030TS/C1:1 | ADC0805S050TS/C1:1 | ADC0801S040TS/C1:1 | ADC0804S040TS/C1 | ADC0804S030TS/C1:1 |
|---|---|---|---|---|---|---|
| Package | 28-SSOP (SOT341-1) | 28-SSOP (SOT341-1) - same | 28-SSOP (SOT341-1) - same | 28-SSOP (SOT341-1) - same | 28-SSOP (SOT341-1) - same | 28-SSOP (SOT341-1) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit |
| Sampling Rate | 40 MSPS | 30 MSPS | 50 MSPS | 40 MSPS | 40 MSPS | 30 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Output Interface | Parallel TTL/CMOS | Parallel TTL/CMOS | Parallel TTL/CMOS | Parallel TTL/CMOS | Parallel TTL/CMOS | Parallel TTL/CMOS |
| Supply Voltage | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Output Bit Code | Offset Binary | Offset Binary | Offset Binary | Offset Binary | Offset Binary | Offset Binary |
主な差別化要因
- 40 MSPS sweet-spot speed for SDTV/IF undersampling （vs ADC0803S030TS/C1:1)
- Mature, multi-source 8-bit video ADC family （vs Newer 12-/14-bit ADC families)
- Direct compatibility with NXP/Renesas legacy designs （vs Third-party 8-bit ADCs)
設計ノート
Separate analog (AGND) and digital (DGND) ground planes connected only at a single point near the ADC ground pins. Place the input anti-alias filter, drive op-amp, and bypass capacitors (100 nF + 10 uF) within 5 mm of the analog pins. Route the 8 parallel output traces with matched lengths (within 50 mil) to the FPGA or capture buffer to minimize skew at 40 MSPS. Estimated: at 40 MSPS, 1 ns of mismatch corresponds to one LSB at the output, so trace-to-trace length matching is critical.
Drive the analog input with a wide-bandwidth op-amp such as the ADA4862-3 or LMH6702 capable of settling to 8 bits within the 25 ns sample period. Add a 50 ohm source-terminated anti-alias filter at the input. Use a low-jitter clock source (under 5 ps RMS jitter); at 40 MSPS the SNR degrades roughly 1 dB per 4 ps of clock jitter per the manufacturer datasheet.
Decouple VDDA and VDDD separately with 100 nF ceramic capacitors as close to each supply pin as possible, plus a shared 10 uF tantalum or ceramic bulk capacitor. The 5V analog and digital rails should be generated from a low-noise LDO (e.g. TPS7A4701) rather than directly from a switching converter, to avoid coupling switching noise into the analog input. Estimated: total supply current is typically 30-50 mA at 40 MSPS per the ADC0806030/040/050 family datasheet.
Do not exceed the absolute maximum analog input range (typically VRT to VRB). Ensure the reference voltage pins (VRT, VRB) are properly bypassed with 100 nF + 10 uF caps. The clock input is sensitive to over-voltage; clamp with a series resistor if driving from a 3.3V logic source while the ADC runs on 5V. Avoid leaving the OE pin floating - tie it to DGND through a 10 kohm resistor if not driven actively.
コンプライアンス情報
RoHS compliant per partstack / alldatasheet JEDEC JESD-609 e3 matte-tin finish. Commercial screening level (0C-70C). Not AEC-Q100 qualified - this part targets industrial/professional video, not automotive. REACH compliance assumed for NXP parts but not explicitly confirmed in the verified data.
