ADSP-2173BS-80 - 24-Bit DSP, 128-Pin PQFP | Analog Devices
部品番号: ADSP-2173BS-80 ✓ 生産中ADSP-2173BS-80 概要
A digital signal processor is a specialized microprocessor whose internal architecture is optimized for repeated mathematical operations on sampled signals. Unlike a general-purpose CPU, the ADSP-2173 family concentrates processing resources on arithmetic, data movement, and real-time control. The ADSP-2173, ADSP-2171, and ADSP-2172 devices share this high-speed processing platform while providing different peripheral combinations for dedicated numeric-processing designs.
The ADSP-2173BS-80 integrates a 16-bit fixed-point arithmetic core, program and data memory, address-generation logic, interrupt and power-management circuitry, and communication interfaces. The advertised 33 MIPS performance at a 16.67 MHz crystal corresponds to the documented 30 ns instruction-cycle time. Two serial ports support synchronous or asynchronous peripheral transfers, while the host port permits interaction with an external host processor in multi-chip systems.
Manufactured using a high-speed, double-metal, low-power CMOS process, the ADSP-2173 family is intended to deliver strong processing efficiency in a compact 128-lead package. The 24-bit external data architecture in the catalog description supports wider data handling than the internal fixed-point arithmetic width, while dedicated address generators reduce the overhead associated with circular buffers, waveform tables, and multidimensional arrays.
Typical applications include industrial motor and motion control, audio and communications signal processing, instrumentation, industrial automation, and embedded systems that require deterministic numeric computation. Its serial interfaces can connect converters, transceivers, codecs, or peripheral ICs, while the host-port architecture allows it to operate as a dedicated real-time processing engine rather than the sole system controller.
Hardware design should account for the external clock source, required program-memory configuration, decoupling, signal-conditioning networks, and the high pin count of the PQFP package. Because the 128-lead footprint is not lead-free compact, new designs should compare board area and assembly complexity against newer fine-pitch DSP or mixed-signal processors before committing to a production layout.
This product record combines the manufacturer’s family description, package and processing details, interface characteristics, sourcing information, and practical implementation guidance. It also identifies same-package ADSP-217x family alternatives for legacy-product evaluation while clearly distinguishing documented drop-in candidates from broader functional comparisons.
ドロップイン代替品: ADSP-2173BS-80 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
ADSP-2171BS-80
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADSP-2172BS-80
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADSP-2173BS-100
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADSP-2173BS-120
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADSP-2173BS-160
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADSP-2173BS-80 仕様
| Device Type | 1 digital signal processor microcomputer |
| Processor Word Length | 24 bit |
| Internal Arithmetic Width | 16 bit |
| Rated Clock Frequency | 10 MHz |
| Instruction Cycle Time | 30 ns |
| Maximum Instruction Rate | 33 MIPS |
| Crystal Frequency for 33 MIPS | 16.67 MHz |
| Serial Port Count | 2 ports |
| Host Port | 1 host port |
| パッケージ | 128-pin plastic PQFP |
| Package Pin Count | 128 pins |
| 実装タイプ | Surface mount |
| Process Technology | High-speed, double-metal, low-power CMOS |
| 電源電圧 | 5 V |
ADSP-2173BS-80 128 pins ピン配置ガイド
ADSP-2173BS-80 (128 pins パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: ADSP-2173BS-80.
詳細は データシート をご参照ください。
主な用途
ADSP-2173BS-80 の用途: 6 件s: Industrial Motor Control, Audio Signal Processing, Communications Modulation, Precision Instrumentation, Data Acquisition Systems, Embedded Control Systems.
Industrial Motor Control
The ADSP-2173BS-80 fits deterministic motor-control loops that depend on fast instruction execution and dedicated numeric processing. Its documented 30 ns instruction cycle can support 33 MIPS operation with the cited 16.67 MHz crystal configuration, while two serial ports can connect position feedback or a host controller. The DSP may execute current-loop and speed-loop algorithms, although the power stage, position sensor, analog front end, protection logic, and safety system remain separate hardware responsibilities. Because the package uses 128 leads, layout should minimize trace lengths around clock and memory signals and provide local decoupling. Firmware should also account for deterministic interrupt latency and verify timing at the highest clock and temperature conditions specified by the manufacturer.
おすすめ
Audio Signal Processing
The ADSP-2173BS-80 is appropriate for real-time audio filtering, mixing, equalization, or other fixed-point signal operations when predictable execution time is important. The 30 ns instruction-cycle architecture and 16-bit internal arithmetic provide a direct path for common digital filter kernels, while the host port allows a separate processor to manage files, control commands, or system-level functions. Two serial ports can link the DSP to audio converters or synchronous interface devices. Board design should isolate converter clocks from sensitive signal paths, provide multiple decoupling capacitors near the supply pins, and route analog and digital returns carefully. Firmware designers should also evaluate overflow, rounding, coefficient quantization, and real-time scheduling rather than relying only on nominal processor throughput.
おすすめ
Communications Modulation
The ADSP-2173BS-80 can serve as a dedicated communications processor for modulation, demodulation, filtering, spectral processing, and bit-oriented protocol work. Its 33 MIPS capability under the documented clock configuration provides substantial arithmetic throughput for repeated multiply-accumulate operations, while the serial ports can support converters, codecs, or transceivers. The host port is useful when another processor handles network management and the DSP performs time-critical waveform processing. A practical design should include controlled clock distribution, terminated or properly referenced interfaces, impedance-controlled routing, and separate analog supply treatment where a transceiver is present. Firmware must confirm that interrupt latency, buffer boundaries, and DMA-style data movement satisfy the protocol timing budget under worst-case traffic.
おすすめ
Precision Instrumentation
The ADSP-2173BS-80 is suitable for measurement and instrumentation systems in which sampled data requires deterministic filtering, calibration, curve fitting, or numerical compensation. The family’s high-speed numeric-processing focus supports short processing windows, while the two serial ports and host port provide flexible separation between acquisition, real-time processing, and a supervisory controller. Instrumentation designs should use low-noise references, shielded analog inputs, isolated dividers where required, and a ground strategy that prevents digital switching currents from entering sensitive measurement paths. Firmware should preserve coefficient precision and define rounding behavior consistently. The 128-pin package also demands careful fanout planning, especially if the board cannot be densely populated or if signal-integrity constraints require controlled-impedance routing.
おすすめ
Data Acquisition Systems
The ADSP-2173BS-80 can act as the real-time processing engine in a multi-channel data-acquisition system, applying filtering, scaling, and calibration after conversion. Its 30 ns instruction cycle allows deterministic processing between acquisition events, and the host port permits results and control commands to be exchanged with a host processor. Two serial ports may connect converters or other data sources, but the electrical interface and protocol timing must be verified for the selected peripheral. Layout should provide a quiet analog section, short return paths for converter signals, local regulator and capacitor placement at every supply pin, and controlled clock routing. Firmware should implement buffer-overrun detection, coherent timing, calibration storage, and graceful handling of overflow or sensor fault conditions.
おすすめ
Embedded Control Systems
The ADSP-2173BS-80 is appropriate for embedded systems that combine deterministic control with dedicated signal processing, especially when a general-purpose host is undesirable. The host port allows supervisory communication, and the two serial ports support external sensors, converters, or actuators. Its 33 MIPS throughput can support multiple concurrent numerical tasks when the firmware scheduler is designed for bounded interrupt latency. Engineers should budget clock margin for temperature and supply variation, avoid placing high-current switching loads near the DSP supply network, and validate every peripheral assignment against the manufacturer pin table. The 128-pin PQFP footprint may be acceptable for legacy industrial control boards, but a new compact design should also compare the cost, routing effort, assembly yield, and software migration burden against newer fine-pitch processors.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADSP-2173BS-80 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADSP-2171BS-80 | ADSP-2172BS-80 | ADSP-2173BS-100 | ADSP-2173BS-120 | ADSP-2173BS-160 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | PQFP-128 | PQFP-128 | PQFP-128 | PQFP-128 | PQFP-128 | PQFP-128 |
| Device Type | DSP microcomputer | DSP microcomputer | DSP microcomputer | DSP microcomputer | DSP microcomputer | DSP microcomputer |
| Processor Word Length | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit |
| Internal Arithmetic Width | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Process Technology | High-speed, double-metal, low-power CMOS | High-speed, double-metal, low-power CMOS | High-speed, double-metal, low-power CMOS | High-speed, double-metal, low-power CMOS | High-speed, double-metal, low-power CMOS | High-speed, double-metal, low-power CMOS |
主な差別化要因
- Exact ADSP-2173 feature variant （vs ADSP-2172BS-80)
- Lower clock operating point in the named suffix （vs ADSP-2173BS-120)
- Dedicated numeric-processing architecture （vs AT91SAM4S16C-ATU)
設計ノート
Treat the 128-pin PQFP footprint as a high-pin-count routing problem. Assign the pinout only from the manufacturer pin-description table, keep clock and high-speed memory routes short, and place bypass capacitors close to the associated supply terminals. Because the package has closely spaced leads on all four sides, verify the PCB design rules, solder-mask clearance, paste volume, assembly inspection access, and board-edge spacing before release.
Provide a clean, low-impedance clock network and keep the external crystal or oscillator path away from switching nodes and analog inputs. Series damping, source termination, or isolation may be needed depending on the physical topology and clock edge rate. Validate settling time and jitter at the DSP clock pin with the final board configuration; a short schematic trace alone does not guarantee adequate timing margin in a 128-pin system.
Budget the 5 V rail for the processor, external interface devices, and inrush behavior rather than applying a single regulator rating without load analysis. Use local decoupling at every supply group, provide adequate bulk capacitance near the regulator, and keep switching regulators and inductors away from sensitive analog sections. Estimated: actual regulator sizing requires the maximum DSP current, peripheral current, allowable voltage drop, and regulator efficiency; those values are not stated here.
Do not treat a shared package as proof of interchangeability. Before fitting an alternative, compare pin names, power pins, clock inputs, serial-port multiplexing, memory and host-port behavior, reset requirements, boot or program-memory options, and absolute timing ratings. Also review software support, peripheral configuration, and development-tool compatibility. A drop-in PCB decision and a working firmware migration are separate engineering gates.
コンプライアンス情報
No explicit RoHS, REACH, lead-free, halogen-free, or conflict-minerals declarations were identified for this exact ordering code. AEC-Q100 qualification is not applicable because the ADSP-2173 is a digital signal processor rather than an automotive-qualified device.
