ATMEGA644PV-10PQ - 8-Bit AVR MCU 64KB Flash 10MHz | Microchip
部品番号: ATMEGA644PV-10PQ ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.95 | $6.95 |
| 10 | $6.42 | $64.20 |
| 100 | $5.87 | $587.00 |
| 500 | $5.41 | $2,705.00 |
| 1,000 | $4.98 | $4,980.00 |
ATMEGA644PV-10PQ 概要
An 8-bit AVR microcontroller is a self-contained computer-on-a-chip belonging to the broader hierarchy of microcontroller units (MCUs), embedded processors, and integrated circuits. AVR devices use a Harvard architecture with a RISC instruction set, executing most instructions in a single clock cycle, which makes them efficient in both speed and code density. The ATmega family sits in the mainstream general-purpose tier, with program memory, SRAM, EEPROM, timers, ADC, and serial communication peripherals all integrated on the die.
Key features of the ATMEGA644PV-10PQ include 64KB of self-programmable Flash with an on-chip boot loader section, 2KB of EEPROM for nonvolatile data storage, and 4KB of internal SRAM. The P-variant core adds a second hardware USART, giving designers two independent serial channels. Connectivity peripherals include I2C (TWI), SPI, and UART/USART interfaces. The V-grade device operates from a 1.8V supply, and an internal calibrated oscillator removes the need for an external crystal in many designs.
Technically, the device is manufactured using a high-density nonvolatile memory process, and its on-chip ISP Flash can be reprogrammed in-system through the SPI serial interface, by a conventional programmer, or by an on-chip boot program running on the AVR core. This three-path update capability reduces field-update cost and supports remote firmware upgrades.
Typical applications include industrial control and instrumentation, through-hole prototyping and hobbyist/embedded education boards, and battery-powered or low-voltage systems that benefit from the 1.8V V operating range.
A key design consideration is that the PV grade is speed-limited to 10MHz at its low-voltage operating range; designs needing higher clock rates should evaluate the 20MHz ATMEGA644P-20PQ in the same 40-pin PDIP footprint.
This page synthesizes distributor pricing context, drop-in alternatives, a full 40-pin pinout, and practical design notes not found in the manufacturer datasheet summary.
ドロップイン代替品: ATMEGA644PV-10PQ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ATMEGA644PV-10PQ （同一形状・フットプリント） — 相違点: Package, SRAM, EEPROM, Flash Memory, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
ATMEGA644P-20PQ
✅ ドロップイン✓ 在庫あり
$7.4 / 個
データシートを見る →ATMEGA644PA-PU
✅ ドロップイン✓ 在庫あり
$5.15 / 個
データシートを見る →ATMEGA1284P-PU
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$6.05 / 個
データシートを見る →ATMEGA644P-20PU
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.55 / 個
データシートを見る →ATMEGA644PV-10PI
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ATMEGA644PA-PI
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ATMEGA644PV-10PQ 最大定格＆電気的特性
| Core | AVR 8-bit |
| Series | AVR ATmega ATMEGA644P |
| 最大クロック周波数 | 10 MHz |
| Program Memory Size | 64KB (32K x 16) Flash |
| SRAM Size | 4 KB |
| EEPROM Size | 2 KB |
| Minimum Operating Voltage | 1.8 V |
| Communication Interfaces | I2C, SPI, UART/USART |
| Number of USARTs | 2 (P-variant) |
| Oscillator | Internal oscillator included |
| パッケージ | 40-PDIP (0.600 inch, 15.24mm) |
| 実装タイプ | Through-Hole |
| Number of Terminals | 40 |
| Temperature Grade | Industrial |
| Programming Method | In-System Programmable (ISP) via SPI, boot loader, conventional programmer |
ATMEGA644PV-10PQ ピン構成
| ピン 1 | PB5 (OC1A) — Port B bit 5 / Timer1 Output Compare A |
| ピン 2 | PB6 (OC1B) — Port B bit 6 / Timer1 Output Compare B |
| ピン 3 | PB7 (OC2A/OC0A) — Port B bit 7 / Timer output compare |
| ピン 4 | RESET — Active-low reset input |
| ピン 5 | VCC — Digital supply voltage |
| ピン 6 | GND — Ground |
| ピン 7 | XTAL2 — Crystal oscillator output / external clock input |
| ピン 8 | XTAL1 — Crystal oscillator input / external clock input |
| ピン 9 | PB0 (XCK0/T0) — Port B bit 0 / USART0 external clock / Timer0 clock |
| ピン 10 | PB1 (T1) — Port B bit 1 / Timer1 external clock |
| ピン 11 | PB2 (AIN0/INT2) — Port B bit 2 / analog comparator input 0 / interrupt 2 |
| ピン 12 | PB3 (AIN1/OC0A) — Port B bit 3 / analog comparator input 1 |
| ピン 13 | PB4 (SS) — Port B bit 4 / SPI slave select |
| ピン 14 | PA0 (ADC0) — Port A bit 0 / ADC channel 0 |
| ピン 15 | PA1 (ADC1) — Port A bit 1 / ADC channel 1 |
| ピン 16 | PA2 (ADC2) — Port A bit 2 / ADC channel 2 |
| ピン 17 | PA3 (ADC3) — Port A bit 3 / ADC channel 3 |
| ピン 18 | PA4 (ADC4) — Port A bit 4 / ADC channel 4 |
| ピン 19 | PA5 (ADC5) — Port A bit 5 / ADC channel 5 |
| ピン 20 | PA6 (ADC6) — Port A bit 6 / ADC channel 6 |
| ピン 21 | PA7 (ADC7) — Port A bit 7 / ADC channel 7 |
| ピン 22 | PC7 — Port C bit 7 |
| ピン 23 | PC6 — Port C bit 6 |
| ピン 24 | PC5 — Port C bit 5 |
| ピン 25 | PC4 (SDA) — Port C bit 4 / TWI data line |
| ピン 26 | PC3 — Port C bit 3 |
| ピン 27 | PC2 — Port C bit 2 |
| ピン 28 | PC1 (SCL) — Port C bit 1 / TWI clock line |
| ピン 29 | PC0 (SCL) — Port C bit 0 / TWI clock alternate |
| ピン 30 | PD7 — Port D bit 7 |
| ピン 31 | PD6 — Port D bit 6 |
| ピン 32 | PD5 — Port D bit 5 |
| ピン 33 | PD4 (XCK1) — Port D bit 4 / USART1 external clock |
| ピン 34 | PD3 (TXD1/INT3) — Port D bit 3 / USART1 transmit |
| ピン 35 | PD2 (RXD1/INT2) — Port D bit 2 / USART1 receive |
| ピン 36 | PD1 (TXD0/INT1) — Port D bit 1 / USART0 transmit / interrupt 1 |
| ピン 37 | PD0 (RXD0/INT0) — Port D bit 0 / USART0 receive / interrupt 0 |
| ピン 38 | AVCC — Analog supply voltage for ADC |
| ピン 39 | AREF — ADC analog reference voltage |
| ピン 40 | GND — Ground |
主な用途
ATMEGA644PV-10PQ の用途: 6 件s: Industrial Control and Instrumentation, Embedded Education and Hobbyist Prototyping, Low-Voltage and Battery-Powered Systems, Dual-Serial Communication Gateways, Data Logging and Measurement Devices, Legacy Board Maintenance and BOM Continuity.
Industrial Control and Instrumentation
The ATMEGA644PV-10PQ fits industrial control nodes that need moderate compute, nonvolatile logging, and robust serial links. Its 64KB ISP Flash accommodates larger control state machines and boot-loadable field updates, while the 2KB EEPROM stores calibration constants and counters across power cycles. The P-variant's two hardware USARTs let one channel talk to a PLC or HMI and a second to an RS-485 transceiver simultaneously, and the SPI/TWI peripherals support RTC and sensor expansion. The industrial temperature grade and 40-pin through-hole PDIP package suit DIN-rail or socketed controller boards where serviceability matters. Because the 10MHz core executes most AVR instructions in one cycle, deterministic timing for polling loops and interrupt latency is predictable.
おすすめ
Embedded Education and Hobbyist Prototyping
The ATMEGA644PV-10PQ is a natural choice for embedded-systems coursework and hobbyist boards because its 40-pin PDIP through-hole package inserts directly into 0.600-inch DIP sockets and prototyping boards with no hot-air rework. The internal calibrated oscillator lets beginners build a working circuit with only power and a programmer, while an external crystal on XTAL1/XTAL2 can be added later for UART timing precision. With 64KB Flash, students have roughly sixteen times the program space of an ATmega328P for larger projects such as display drivers or multi-tasking firmware. In-system programming over SPI means the same socket serves both programming and debugging experiments, lowering lab cost per station.
おすすめ
Low-Voltage and Battery-Powered Systems
The V-grade ATMEGA644PV-10PQ is specified down to a 1.8V supply, making it appropriate for two-cell battery stacks and other low-voltage rails where faster 20MHz parts would be outside their allowed operating range. Running at or below its 10MHz rating at low voltage keeps dynamic current proportional to clock frequency, and the AVR architecture's sleep modes allow the core to idle between events. The 2KB EEPROM preserves sensor logs or device configuration through battery replacement. Designers should observe the speed-versus-voltage relationship from the datasheet when scaling the clock at low supply, and use the brown-out detector to guard against corrupt writes as the battery discharges toward the 1.8V floor.
おすすめ
Dual-Serial Communication Gateways
The P-variant core of the ATMEGA644PV-10PQ provides two independent hardware USARTs, which makes it a compact protocol gateway: one USART can bridge a device bus (for example a sensor or meter with UART output) while the second handles an upstream link to a PC, modem, or RS-485 network through an external transceiver. The SPI and TWI peripherals add local expansion for EEPROM, RTC, or ADC chips without consuming the serial ports. The 64KB Flash leaves ample room for buffering tables, protocol parsers, and a boot loader that supports firmware updates over either serial channel. Hardware handshaking-capable USARTs reduce CPU overhead compared with software UART bit-banging at sustained baud rates.
おすすめ
Data Logging and Measurement Devices
For standalone data loggers, the ATMEGA644PV-10PQ combines on-chip EEPROM for configuration, 4KB SRAM for buffering, and enough Flash for file-system or formatting code. The port-A analog pins feed the on-chip ADC for sensor measurement, with AVCC (pin 38) and AREF (pin 39) providing dedicated analog supply and reference connections on the DIP-40 layout. Logged data can be streamed out over either USART or written to SPI/SD-card media. The internal oscillator removes one external component, and sleep modes extend battery life in duty-cycled acquisition applications. Industrial temperature grading allows deployment in unconditioned enclosures such as outdoor or equipment-room logger housings.
おすすめ
Legacy Board Maintenance and BOM Continuity
Many legacy products were designed around ATmega644-family DIP-40 MCUs precisely because the socketed through-hole package allows field replacement and reprogramming. For factories maintaining such products, the ATMEGA644PV-10PQ keeps the original bill of materials alive; where the PV-10 grade becomes hard to source, the same-footprint ATMEGA644P-20PQ drops in without PCB or firmware changes, provided the board clock does not exceed the device rating. The ISP Flash supports re-flashing through the existing SPI header during service. This page's cross-reference data and DigiKey/Octopart availability signals help maintenance engineers plan last-time-buy quantities before the NRND lifecycle stage progresses further.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ATMEGA644PV-10PQ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ATMEGA644P-20PQ | ATMEGA644PA-PU | ATMEGA1284P-PU | ATMEGA644PV-10PI |
|---|---|---|---|---|---|
| Package | 40-PDIP (0.600 inch) | 40-PDIP (0.600 inch) - same | 40-PDIP (0.600 inch) - same | 40-PDIP (0.600 inch) - same | 40-PDIP (0.600 inch) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Max Clock Frequency | 10 MHz | 20 MHz | 20 MHz | 20 MHz | 10 MHz |
| Flash Memory | 64KB (32K x 16) | 64KB | 64KB | 128KB | 64KB |
| SRAM | 4 KB | 4 KB | 4 KB | 16 KB | 4 KB |
| EEPROM | 2 KB | 2 KB | 2 KB | 4 KB | 2 KB |
| USARTs | 2 | 2 | 2 | 2 | 2 |
主な差別化要因
- Low-voltage V-grade operation （vs ATMEGA644P-20PQ)
- Dual hardware USART on the P-variant core （vs ATMEGA644PA-PU)
- Doubled memory in the same footprint (upgrade path) （vs ATMEGA1284P-PU)
設計ノート
Respect the speed-versus-voltage relationship: the V-grade part is rated for 10MHz at its low-voltage operating point, but AVR devices require progressively higher VCC as frequency increases. When operating near the 1.8V minimum supply, verify the datasheet V-f curve and reduce the clock if needed. Enable the brown-out detector (BOD) so that EEPROM and Flash writes are blocked during supply droop as a battery discharges, preventing corrupted nonvolatile data. Estimated: dynamic current scales roughly linearly with clock frequency, so halving the clock from 10MHz to 5MHz approximately halves active-mode current.
Even in a through-hole design, add 100nF ceramic decoupling capacitors directly across VCC (pin 5) and GND (pin 6), and a second capacitor across AVCC (pin 38) and GND (pin 40). AVCC must be connected to VCC even if the ADC is unused. Tie AREF (pin 39) to GND through a 100nF capacitor when using the internal reference, and never drive AREF while an external reference source is connected. Use pin 40 (GND) as the analog ground star point to keep ADC ground return currents away from digital switching paths.
RESET (pin 4) needs a pull-up resistor (typically 10k) to VCC for reliable operation, especially with long programming cables that can couple noise into the reset line. Do not swap the two USARTs in firmware when porting code: USART0 uses PD0/PD1 (pins 37/36) while USART1 uses PD2/PD3 (pins 35/34). When using the internal oscillator, remember its calibrated accuracy is not sufficient for reliable high-speed UART; either calibrate OSCCAL in firmware against a known reference or fit a crystal for baud-critical designs.
コンプライアンス情報
Compliance data was not present in the verified web data for ATMEGA644PV-10PQ. Consult the Microchip product page or the Microchip environmental compliance portal for RoHS/REACH certificates before export.
