CD4059AM - Programmable Divide-by-N CMOS Counter | Texas Instruments
部品番号: CD4059AM ✓ 生産中CD4059AM 概要
A divide-by-N counter is a sequential digital logic device that counts clock transitions and reaches a programmable terminal count before producing an output event. The CD4059AM belongs to the CD4000 CMOS logic family, where CMOS indicates complementary metal-oxide-semiconductor construction. In system terms, it is a programmable counter, a digital timing IC, and a member of the wider logic IC and clock-and-timing categories. Its primary purpose is to reduce an input clock into a lower, predictable frequency without requiring a microcontroller or discrete counter chain.
The main engineering features are the broad programmable division range, 16-bit internal counting capacity, positive-edge operation, and 24-SOIC packaging. The programmable range allows a fixed board design to support several timing ratios simply by changing the logic states applied to the count-select pins. The CMOS implementation is suitable for digital systems where low static power and direct interfacing to other CMOS logic are important, although the exact timing and supply-current limits should be taken from the manufacturer datasheet for the operating condition being designed.
The CD4059AM can be used for pulse-rate reduction, timer generation, clock division, sequential timing, digital measurement, and embedded control systems. It is especially useful when a stable clock must be converted into a slower periodic signal without consuming processor resources. In an industrial controller, it can divide a high-frequency system clock to produce a service-timing or sampling interval. In a laboratory instrument, it can reduce a reference clock for a programmable pulse output. The output pulse timing and reset behavior must be coordinated with the surrounding synchronous logic.
The principal design consideration is ensuring that the programmed count remains within the permitted range of 3 to 15,999 and that the clock and reset inputs meet the datasheet timing requirements. Because the device is a fixed-function counter rather than a general-purpose programmable logic device, design changes requiring arbitrary counter widths, multiple independent channels, or complex arithmetic may be better served by a different logic family. The 24-SOIC package also requires a footprint with the correct pin pitch and exposed mechanical dimensions.
This product page combines the manufacturer identification, counter-function description, programming limits, package information, pinout availability, practical applications, and design trade-offs for engineers evaluating the CD4059AM. It also distinguishes true same-footprint alternatives from parts that may be functionally similar but are not qualified as direct replacements.
ドロップイン代替品: CD4059AM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
CD4059AM96
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD4059AMG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD74HC4059E
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD4059AM 最大定格＆電気的特性
| Product Type | CMOS Programmable Divide-by-N Counter |
| Counter Configuration | 1 Element |
| Counter Width | 16 Bit |
| Counting Direction | Down-Counter |
| Counting Edge | Positive Edge |
| Programmable Division Range | N = 3 to 15,999 |
| Logic Family | CD4000 CMOS Series |
| Supply Voltage Range | 3 V to 18 V |
| パッケージ | 24-Lead Small-Outline Integrated Circuit (SOIC) |
| 実装タイプ | Surface Mount |
| Output Signal | One-Clock-Wide Pulse at Input Frequency Divided by N |
| Programming Inputs | 5 Dedicated Divide-By-N Program Inputs |
| Datasheet Revision | Rev. B |
| Manufacturer | Texas Instruments |
CD4059AM 24-lead small-outline integrated circuit (soic) ピン配置ガイド
CD4059AM (24-lead small-outline integrated circuit (soic) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: CD4059AM.
詳細は データシート をご参照ください。
主な用途
CD4059AM の用途: 6 件s: Programmable Clock Division, Industrial Pulse-Timer Service, Digital Test and Measurement, Automotive Lighting and Flash Sequencing, Portable Device Rate Generation, Frequency Divider for Communication Modules.
Programmable Clock Division
The CD4059AM is well suited to reducing a system clock because its five count-program inputs select a division ratio from 3 to 15,999 while the 16-bit counter produces a one-clock-wide output pulse. Place the device between the source clock and the receiving logic, then drive the count-select pins with stable CMOS-compatible states. This approach lowers processor timer workload and provides a hardware-defined time base. During design, confirm the clock period against the manufacturer's timing limits and ensure that count-select transitions do not violate the required setup and hold interval.
おすすめ
Industrial Pulse-Timer Service
In an industrial controller, the CD4059AM can divide a stable periodic clock into a slower service or sampling interval without allocating a software timer. Its programmable range of 3 to 15,999 makes it useful where multiple maintenance, flashing, or periodic-task rates must be selected digitally. Encode the desired ratio through the five programming inputs and use the output pulse to trigger downstream synchronous logic. Validate timing margins across voltage and temperature, and add a reset strategy that establishes a known count state at startup.
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Digital Test and Measurement
The CD4059AM can create a divided trigger or repetition rate in a digital test instrument when a low-frequency pulse is required alongside a faster reference clock. The positive-edge counter accepts a periodic input and emits a one-clock-wide pulse after the programmed count interval, providing a repeatable event for sampling or sequencing. Connect the output through the instrument's input-conditioning circuitry and account for threshold, propagation-delay, and load requirements in the timing budget. The 24-SOIC package simplifies retrofit into a surface-mount instrument platform.
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Automotive Lighting and Flash Sequencing
A programmable frequency divider can support repeatable flash, blink, or diagnostic timing sequences in vehicle electronic modules when the system already provides a stable clock. The CD4059AM offers five digitally controlled division settings and a 16-bit counting range, allowing a compact fixed-function implementation. Its 3 V to 18 V supply range is compatible with common logic rails, but automotive use requires checking the exact temperature grade, electrical limits, transient tolerance, and qualification status before production release. A qualified timer or MCU may be preferable for safety-related functions.
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Portable Device Rate Generation
The CD4059AM can divide a low-frequency oscillator into a slower operating cadence for portable equipment, including key scanning, indicator updates, or periodic housekeeping. Because it operates as a dedicated hardware divider, it reduces the need to wake a microcontroller repeatedly for a fixed timing interval. Select a division ratio within the supported 3 to 15,999 range and keep the count-select pins static unless the circuit includes a deliberate safe retiming mechanism. Low power design should also account for the counter's static and dynamic supply current at the selected clock frequency.
おすすめ
Frequency Divider for Communication Modules
The CD4059AM can reduce a communications-module clock to a lower periodic signal for housekeeping, sampling, or protocol timing support. Its positive-edge counting behavior and programmable terminal count are useful when the clock is regular and the required ratio fits the 3 to 15,999 range. Keep the divider output synchronized with the surrounding digital system, and account for propagation delay when using multiple cascaded stages. A dedicated frequency divider or clock generator may offer better jitter control when the output is used directly for high-accuracy communication timing.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: CD4059AM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | CD4059AM96 | CD4059AMG4 | CD74HC4059E |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 24-SOIC | 24-SOIC | 24-SOIC | 24-SOIC |
| Division Range | 3 to 15,999 | 3 to 15,999 | 3 to 15,999 | 3 to 15,999 |
| Logic Family | CD4000 CMOS | CD4000 CMOS | CD4000 CMOS | 74HC CMOS |
| Output Pulse | One Clock Cycle Wide | One Clock Cycle Wide | One Clock Cycle Wide | One Clock Cycle Wide |
| Special Feature | CD4000 CMOS Family | CD4000 CMOS Family | CD4000 CMOS Family | High-Speed 74HC Series |
| Input Interface Compatibility | CD4000 CMOS | CD4000 CMOS | CD4000 CMOS | 74HC Logic Levels |
主な差別化要因
- Broad fixed-function division range （vs CD74HC4059E)
- Closest functional continuity （vs CD4059AM96)
- Same-footprint ordering alternatives （vs CD4059AMG4)
設計ノート
Do not assume that every divide-by-N counter is a direct replacement. The CD4059AM is a CD4000-family CMOS device, whereas the CD74HC4059 uses a different logic family and interface behavior. Before substituting, compare supply voltage, input thresholds, clock-edge timing, reset polarity, output timing, package dimensions, and temperature grade. This is especially important when the original board mixes the counter with TTL-family signals.
The listed operating range is 3 V to 18 V. Design the input signals and programming pins so their logic levels remain valid across the actual supply range and noise environment. The program inputs determine the terminal count and therefore the output ratio; keep them stable around active clock edges, and use reset to establish a known state after power-up. Confirm the acceptable input voltage limits and setup timing in the manufacturer datasheet.
The CD4059AM uses a 24-lead SOIC package, so the PCB land pattern must match the mechanical drawing rather than a 24-pin DIP footprint. Confirm pin pitch, body width, lead span, and solder-paste geometry against the package drawing before fabrication. Place bypass decoupling close to the supply and ground pins and route the clock and programming traces away from noisy switching nodes to reduce false clock edges and count-program glitches.
Treat the clock as a synchronous signal even though the counter is programmable. Maintain a clean rising edge with controlled rise and fall times, and avoid routing it beside high-current switching traces. If the division ratio changes dynamically, synchronize the five program inputs and observe the manufacturer's timing requirements. A static control word is the simplest implementation and reduces the risk of an unintended intermediate count value.
コンプライアンス情報
The available product information identifies the CD4059A family and its 3 V to 18 V operating range but does not state the requested environmental or material-compliance status. AEC-Q100 qualification is not established.
