CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar
部品番号: CDK1307CILP40 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.4 | $6.40 |
| 10 | $5.85 | $58.50 |
| 100 | $5.1 | $510.00 |
| 500 | $4.55 | $2,275.00 |
| 1,000 | $3.95 | $3,950.00 |
CDK1307CILP40 概要
An analog-to-digital converter (ADC) is a data-conversion integrated circuit that samples continuous analog input signals and converts them into discrete digital codes for downstream digital signal processing. The CDK1307 sits inside the data-converter -> signal-chain -> mixed-signal IC hierarchy and is typically paired with a low-noise operational amplifier front-end and a downstream FPGA, DSP, or microcontroller. The "CILP40" suffix encodes both the temperature grade (-40 C to +85 C industrial range) and the 40-pin LQFP package.
Key features per the manufacturer datasheet include a single 3.3 V analog supply, internal 1.2 V reference, CMOS digital outputs, low standby current of 9 mW typical at 65 MSPS, and an external clock input with duty-cycle stabilizer. The converter accepts single-ended analog inputs typically centered at 1.5 V with a 1 Vpp full-scale range, and provides 12-bit or 13-bit selectable resolution through the configuration register.
Architecturally, the CDK1307CILP40 uses a multi-stage pipelined switched-capacitor core with proprietary digital error correction. This pipeline topology enables high sample rates (up to 80 MSPS) at low power consumption by distributing the conversion work across cascaded stages. The internal bandgap-based reference and integrated clock-receiver circuitry minimize external component count.
Typical applications include portable ultrasound front-ends, handheld industrial instrumentation, low-power imaging pipelines, IF/baseband digitizing for software-defined radio, and battery-powered test equipment. Designers also use the CDK1307 in medical patient-monitoring subsystems and portable oscilloscope front-ends where power budget is critical.
Design tip: route the analog and digital grounds as separate nets that join only at the EP/exposed-pad or at the AGND/DGND pin per the datasheet layout example. Place input coupling capacitors close to the AIN pin and bypass AVDD/DVDD with 0.1 uF ceramic + 10 uF tantalum pairs. Maintain a stable low-jitter clock at ENC+/ENC- to avoid degrading SNR.
This page synthesizes distributor stock data, drop-in alternatives, and practical layout guidance not collected in a single place in the manufacturer datasheet.
ドロップイン代替品: CDK1307CILP40 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: CDK1307CILP40 （同一形状・フットプリント） — 相違点: Package, Resolution, Architecture, Manufacturer, Reference.
クイック比較ツール — 並列比較する代替部品を選択:
CDK1307AILP40
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.21 / 個
データシートを見る →CDK1307BILP40
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.22 / 個
データシートを見る →CDK1307DILP40
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.6 / 個
データシートを見る →CDK1308CILP40
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.7 / 個
データシートを見る →CDK1307CILP40 最大定格＆電気的特性
| Part Number | CDK1307CILP40 |
| Manufacturer | MaxLinear (formerly Exar/Cadeka) |
| 機能 | Analog-to-Digital Converter (ADC) |
| 分解能 | 12-bit / 13-bit selectable |
| Sample Rate | 65 MSPS (family supports 20/40/65/80 MSPS) |
| Architecture | Multi-stage pipeline with digital error correction |
| Input Type | Single-ended analog input |
| Full-Scale Input Range | 1 Vpp typical |
| Supply Voltage (Analog) | 3.3 V |
| Supply Voltage (Digital) | 3.3 V |
| Reference | Internal (1.2 V bandgap) |
| Output Interface | Parallel CMOS |
| Control Interface | CMOS serial configuration |
| パッケージ | 40-pin LQFP (LP) |
| 動作温度 | -40 C to +85 C (industrial) |
| RoHS ステータス | Compliant |
CDK1307CILP40 ピン構成
| ピン 1 | AIN — Analog input (single-ended) |
| ピン 2 | AGND — Analog ground return |
| ピン 3 | AVDD — Analog 3.3 V supply |
| ピン 4 | VREF — Internal reference bypass node |
| ピン 5 | AGND — Analog ground |
| ピン 6 | NC — Not connected (per datasheet) |
| ピン 7 | ENC+ — Differential clock input (positive) |
| ピン 8 | ENC- — Differential clock input (negative) |
| ピン 9 | DGND — Digital ground |
| ピン 10 | DVDD — Digital 3.3 V supply |
| ピン 11 | PDWN — Power-down control input |
| ピン 12 | CS — Serial interface chip select |
| ピン 13 | SCLK — Serial configuration clock |
| ピン 14 | SDIO — Serial configuration data I/O |
| ピン 15 | DGND — Digital ground |
| ピン 16 | D0 — CMOS data output bit 0 (LSB) |
| ピン 17 | D1 — CMOS data output bit 1 |
| ピン 18 | D2 — CMOS data output bit 2 |
| ピン 19 | D3 — CMOS data output bit 3 |
| ピン 20 | D4 — CMOS data output bit 4 |
| ピン 21 | D5 — CMOS data output bit 5 |
| ピン 22 | D6 — CMOS data output bit 6 |
| ピン 23 | D7 — CMOS data output bit 7 |
| ピン 24 | D8 — CMOS data output bit 8 |
| ピン 25 | D9 — CMOS data output bit 9 |
| ピン 26 | D10 — CMOS data output bit 10 |
| ピン 27 | D11 — CMOS data output bit 11 |
| ピン 28 | D12 — CMOS data output bit 12 (MSB) |
| ピン 29 | OGND — Output driver ground |
| ピン 30 | OVDD — Output driver supply |
| ピン 31 | NC — Not connected (per datasheet) |
| ピン 32 | AGND — Analog ground |
| ピン 33 | AVDD — Analog 3.3 V supply |
| ピン 34 | NC — Not connected (per datasheet) |
| ピン 35 | NC — Not connected (per datasheet) |
| ピン 36 | NC — Not connected (per datasheet) |
| ピン 37 | NC — Not connected (per datasheet) |
| ピン 38 | NC — Not connected (per datasheet) |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | EP — Exposed thermal pad - tie to AGND |
主な用途
CDK1307CILP40 の用途: 6 件s: Portable Ultrasound Front-End, IF Digitizing for Software-Defined Radio, Handheld Industrial Instrumentation, Low-Power Imaging Pipeline, Battery-Powered Test Equipment, Medical Patient Monitoring Subsystem.
Portable Ultrasound Front-End
The CDK1307CILP40 is well suited to portable ultrasound receiver channels. With 65 MSPS it comfortably samples IF frequencies up to 32 MHz while the 12/13-bit selectable resolution captures the dynamic range needed for echo envelopes. The ultra-low-power pipeline architecture keeps total front-end dissipation low enough for handheld probe assemblies. A typical signal chain pairs the CDK1307 with a low-noise op-amp (such as the AD797 family) feeding AIN, then routes parallel CMOS outputs to an FPGA for beamforming.
おすすめ
IF Digitizing for Software-Defined Radio
In SDR receivers the CDK1307CILP40 serves as the IF digitizer after a quadrature mixer. The 65 MSPS rate covers IF bandwidths up to 32 MHz, sufficient for narrowband and many wideband waveforms. The internal 1.2 V reference eliminates an external reference IC and the parallel CMOS outputs drop directly into an FPGA DSP fabric. The CMOS control interface allows mode switching and standby for battery-saving operation in field radios.
おすすめ
Handheld Industrial Instrumentation
Handheld oscilloscopes, vibration analyzers, and process calibrators use the CDK1307CILP40 as the main acquisition ADC. Its 12/13-bit resolution supports general-purpose waveform capture while the 65 MSPS rate provides 32 MHz of analog input bandwidth. The 40-pin LQFP allows compact PCB layouts and the low standby current extends battery life in field-portable products. An external anti-alias LPF precedes AIN to enforce clean Nyquist sampling.
おすすめ
Low-Power Imaging Pipeline
Line-scan and small-area CMOS imaging systems use the CDK1307CILP40 to digitize analog pixel streams. The 65 MSPS rate supports line rates up to several thousand lines per second, while 12/13-bit resolution preserves color depth and dynamic range. The internal reference and single 3.3 V supply minimize external BOM, critical for compact camera modules. CMOS outputs stream directly to an FPGA image-processing pipeline.
おすすめ
Battery-Powered Test Equipment
Portable data loggers, EMI sniffers, and bench instruments benefit from the CDK1307CILP40 ultra-low-power architecture. At 65 MSPS the standby power stays low enough for hours of battery operation between charges. The 12/13-bit resolution covers most field-measurement needs and the 1 Vpp full-scale input accommodates standard sensor signal levels with simple op-amp scaling. Parallel CMOS outputs feed a small MCU or FPGA for FFT and logging.
おすすめ
Medical Patient Monitoring Subsystem
Patient monitors measuring ECG, SpO2, or respiration waveforms use the CDK1307CILP40 as the primary acquisition ADC. The 65 MSPS rate is more than sufficient for physiological signals (typically under 10 kHz bandwidth) and the 12/13-bit resolution preserves signal fidelity for downstream QRS detection and pulse-oximetry math. The low-power pipeline keeps thermal dissipation low - important for patient-skin-adjacent wearables - and the small 40-pin LQFP fits compact wearable form factors.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: CDK1307CILP40 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | CDK1307AILP40 | CDK1307BILP40 | CDK1307DILP40 | CDK1308CILP40 |
|---|---|---|---|---|---|
| Package | LQFP-40 | LQFP-40 - same | LQFP-40 - same | LQFP-40 - same | LQFP-40 - same |
| Brand | MaxLinear | MaxLinear | MaxLinear | MaxLinear | MaxLinear |
| Resolution | 12/13-bit selectable | 12/13-bit selectable | 12/13-bit selectable | 12/13-bit selectable | 12/13-bit selectable |
| Sample Rate | 65 MSPS | 40 MSPS (-38%) | 20 MSPS (-69%) | 80 MSPS (+23%) | 80 MSPS (+23%) |
| Architecture | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS |
| Supply Voltage | 3.3 V single | 3.3 V single | 3.3 V single | 3.3 V single | 3.3 V single |
| Internal Reference | Yes (1.2 V) | Yes (1.2 V) | Yes (1.2 V) | Yes (1.2 V) | Yes (1.2 V) |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主な差別化要因
- Pin-compatible 4-speed family (20/40/65/80 MSPS) （vs CDK1307AILP40 (40 MSPS grade))
- Ultra-low-power pipeline architecture （vs CDK1308CILP40 (next-gen 80 MSPS))
- Integrated reference and clock receiver （vs Generic 12-bit 65 MSPS ADC (e.g. AD9235 family))
設計ノート
Power the CDK1307CILP40 from a clean 3.3 V LDO or low-noise switching regulator post-filter. Place a 0.1 uF X7R ceramic + 10 uF tantalum bypass pair on each AVDD and DVDD pin, located within 3 mm of the pin. Keep the AVDD/DVDD traces short and isolated with a ferrite bead to prevent digital switching noise coupling back into the analog domain.
Maintain separate analog and digital ground planes that join only at the EP (exposed thermal pad) or at the AGND/DGND pin. Route the ENC+/ENC- differential clock with matched impedance and length matching (within 1 mm) to preserve duty cycle. Keep digital output traces (D0-D12) away from AIN and VREF traces to avoid digital coupling into the analog input.
Drive ENC+/ENC- with a low-jitter, low-phase-noise clock source - clock jitter directly degrades ADC SNR per the formula SNR = 6.02*ENOB + 1.76 + 20*log10(1/(2*pi*Fin* Tjitter)). For 32 MHz analog input and 12-bit performance, total jitter must stay below 5 ps RMS. Add a small RC filter at the clock pins if the source clock has overshoot or ringing.
Do not float the PDWN pin - tie it high (enabled) or low (standby) through a 10 kohm resistor. Do not exceed the maximum 3.6 V on AVDD/DVDD even during power-up transients. Sequence AVDD before DVDD if your design supports it, to avoid latch-up. Reference voltages (VREF) require their own bypass capacitor to AGND, sized per the datasheet (typically 0.1 uF in parallel with 10 uF).
コンプライアンス情報
RoHS and lead-free per MaxLinear product page (2026-10-13). REACH status confirmed via MaxLinear declaration. AEC-Q100 not applicable - this is a commercial/industrial ADC; for automotive applications consult MaxLinear for the AEC-Q100-qualified product line.
