DS90C124IVS - 840 Mbps 24-Bit LVDS Deserializer | Texas Instruments
部品番号: DS90C124IVS ✗ 生産終了DS90C124IVS 概要
An LVDS deserializer is a high-speed interface IC that reconstructs parallel digital data from a low-voltage differential serial signal. Within the interface hierarchy, LVDS signaling belongs to high-speed differential data transmission, while a deserializer is a serializer/deserializer interface IC used to reduce parallel routing, connector-pin count, skew, and PCB-layer requirements. The FPD-Link II chipset architecture carries both data and control information over one serial link while removing the need for a separate source-synchronous clock.
The principal interface ratings are a 5 MHz to 35 MHz pixel-clock range, an 840 Mbps maximum data rate, one LVDS input, 24 parallel outputs, and a 48-TQFP package. According to the Texas Instruments product page and DS90C124 datasheet, the receiver uses differential threshold voltage and input-tolerance switching characteristics to define the acceptable data-eye opening. These signal-integrity limits must be respected when selecting cable length, connector geometry, connector geometry, and receiver termination.
The device is intended to work with the compatible DS90C241 serializer, which converts a 24-bit parallel bus into a transparent DC-balanced LVDS stream. Embedded-clock recovery eliminates a dedicated parallel clock and minimizes skew between separate data and clock paths. The serialized interface can reduce PCB routing demands and connector size compared with a conventional 24-bit parallel bus, although board-level LVDS routing, reference-plane continuity, and pair geometry remain critical.
Typical uses include high-resolution display links, digital video transport, industrial imaging, automotive infotainment, instrumentation, and other point-to-point LVDS systems. The verified source material specifically identifies display-oriented 24-bit FPD-Link II transport and a compatible serializer for a 10-meter shielded twisted-pair cable. An LVDS receiver is most suitable when the source can provide the matching FPD-Link II serializer and when the PCB or cable channel has been validated for the intended data rate.
For implementation, preserve the differential pair as a continuous, impedance-controlled route from the connector or cable through the receiver, provide the decoupling and termination required by the manufacturer datasheet, and validate the received eye diagram at the production operating temperature. The supplied verified material does not provide a numeric price, complete pin mapping, or detailed electrical limits, so those items are not inferred in the specifications or structured product markup.
ドロップイン代替品: DS90C124IVS — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
DS90C124IVS/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90C124IVSX/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90C124IVS
✅ ドロップイン ⚠️ 仕様未検証価格はお問い合わせください
データシートを見る →DS90C124IVS 仕様
| Device Type | 24-bit FPD-Link II LVDS deserializer |
| Pixel Clock Frequency Range | 5 MHz to 35 MHz |
| Maximum Serial Data Rate | 840 Mbps |
| Input Configuration | 1 LVDS differential input |
| Parallel Output Count | 24 outputs |
| Parallel Data Width | 24 bit |
| Signaling Standard | DC-balanced LVDS |
| Clocking Method | Embedded-clock serial stream |
| Companion Serializer | DS90C241 |
| パッケージ | 48-pin TQFP, 7 mm x 7 mm |
| Package Type | TFQFP |
| Terminal Count | 48 |
| 実装タイプ | Surface mount |
| Temperature Grade | Industrial |
| Lead Finish | Lead-free NOPB variant |
| ESD Tolerance | 8 kV HBM |
| Maximum Cable Length | 10 m with compatible DS90C241 over shielded twisted pair |
DS90C124IVS tfqfp ピン配置ガイド
DS90C124IVS (tfqfp パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: DS90C124IVS.
詳細は データシート をご参照ください。
主な用途
DS90C124IVS の用途: 6 件s: High-Resolution Display Interfaces, Industrial Imaging Systems, Digital Video Transport, Automotive Infotainment Link, Test and Measurement Instrumentation, Instrumentation and Control Networks.
High-Resolution Display Interfaces
The DS90C124IVS is appropriate for the receiving endpoint of a 24-bit FPD-Link II display link because it supports a 5 MHz to 35 MHz clock range and reconstructs 24 parallel outputs from one DC-balanced LVDS stream. A DS90C241 serializer can place the embedded-clock data on a compact differential route, reducing wide-bus routing and separate clock skew. The verified chipset material reports 10 m shielded twisted-pair support under suitable channel conditions. Designers should still verify eye margin, connector loss, reference-plane continuity, and worst-case temperature before approving that distance.
おすすめ
Industrial Imaging Systems
Industrial imaging systems can use the DS90C124IVS to carry a 24-bit parallel pixel or control bus across a board-to-board or shielded-cable LVDS connection. Its 840 Mbps serial capability and embedded-clock transport eliminate a separately routed source-synchronous clock and reduce parallel-bus skew exposure. The industrial-temperature classification supports use in industrial equipment, while the receiver’s defined threshold and input-tolerance characteristics provide the basis for channel validation. Layout, cable impedance, and connector selection remain the critical integration variables.
おすすめ
Digital Video Transport
For point-to-point digital video transport, the DS90C124IVS provides a 24-output parallel receiving interface while accepting a single DC-balanced LVDS lane from a DS90C241-compatible source. The 5 MHz to 35 MHz operating range accommodates a defined class of parallel pixel clocks, and the 840 Mbps maximum data rate provides a clear ceiling for system timing analysis. Because the protocol is transparent and clock information is embedded, the design avoids separate data and clock skew; engineers must still validate video timing, link startup, and cable loss at production extremes.
おすすめ
Automotive Infotainment Link
The DS90C124IVS can serve as a receiver in an automotive infotainment or display transmission architecture when paired with the DS90C241 chipset and the complete design satisfies automotive qualification requirements. Its single-input, 24-output LVDS interface supports compact point-to-point wiring, while the verified material reports an industrial temperature grade and 8 kV HBM ESD tolerance. However, the supplied source does not explicitly establish AEC-Q100 qualification for the exact MPN, so automotive release requires additional qualification, EMC, transient, and temperature evidence.
おすすめ
Test and Measurement Instrumentation
The DS90C124IVS can replace a wide parallel data path in instrumentation that distributes 24-bit control, status, or acquisition data between circuit boards. Serializing the bus with a compatible DS90C241 can reduce connector pins and board-routing congestion while embedded-clock operation removes a separate clock path. The design remains suitable only when the instrument’s data rate falls within the 5 MHz to 35 MHz interface range and the receiver’s data-eye opening remains adequate after losses from cables, connectors, protection devices, and board traces.
おすすめ
Instrumentation and Control Networks
The DS90C124IVS can serve in industrial control or monitoring equipment that needs a compact, low-noise differential link between a controller and a remote I/O or processing board. The DS90C241/DS90C124 chipset translates a 24-bit parallel bus into one transparent serial stream, helping reduce parallel-layer demand and connector size while carrying embedded clock information. For deployment, engineers should check receiver threshold margins, cable shielding, grounding, and system-level reset timing so that power sequencing does not create an invalid differential state during startup.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DS90C124IVS — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DS90C124IVS/NOPB | DS90C124IVSX/NOPB | DS90C124IVS |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (7 mm x 7 mm) | 48-TQFP (7 mm x 7 mm) | 48-TQFP (7 mm x 7 mm) | 48-TQFP (7 mm x 7 mm) |
| Function | 24-bit FPD-Link II LVDS deserializer | 24-bit FPD-Link II LVDS deserializer | 24-bit FPD-Link II LVDS deserializer | 24-bit FPD-Link II LVDS deserializer |
| Clock Frequency Range | 5 MHz to 35 MHz | 5 MHz to 35 MHz | 5 MHz to 35 MHz | 5 MHz to 35 MHz |
| Maximum Serial Data Rate | 840 Mbps | 840 Mbps | 840 Mbps | 840 Mbps |
| LVDS Input Count | 1 differential input | 1 differential input | 1 differential input | 1 differential input |
| Parallel Output Count | 24 outputs | 24 outputs | 24 outputs | 24 outputs |
| Compatible Serializer | DS90C241 | DS90C241 | DS90C241 | DS90C241 |
主な差別化要因
- Complete 24-bit receive interface （vs DS90C124IVS/NOPB)
- Wide supported clock range （vs DS90C124IVSX/NOPB)
- Embedded-clock link architecture （vs DS90C124IVS/NOPB)
設計ノート
Treat the DS90C124 LVDS pair as a controlled-impedance route from the source through every connector to the receiver. Avoid stubs, test pads without loading, and changes in reference geometry; keep the two traces coupled and maintain the intended distance to a continuous reference plane. Because the manufacturer identifies differential threshold voltage and receiver input tolerance as the limits defining the acceptable data eye, validate the eye diagram at the receiver pins using the longest cable, worst-case connectors, and production temperature limits.
Place the DS90C124IVS close to the cable or channel entry to minimize trace loss and reduce susceptibility to interference. Follow the manufacturer datasheet for the exact bypass-capacitor placement, receiver termination, supply routing, and unused-pin connections. Provide a solid ground or reference plane beneath the LVDS route and keep switching converters, clocks, and other high-current nets physically separated. These layout controls are necessary because an apparently correct schematic can still fail when connector and package transitions distort the receiver eye.
Use the manufacturer-defined supply voltage and decoupling values for the DS90C124IVS rather than deriving them from the DS90C241 transmitter requirements. Confirm supply sequencing, startup behavior, and the differential input state during power transitions so the receiver is not exposed to an invalid long-term differential condition. The verified source does not provide the numerical supply range or current limits, so this note intentionally does not substitute estimated values for missing ratings.
Do not select a substitute solely because it is described as a 24-bit LVDS receiver. The DS90C124 is part of the DS90C241/DS90C124 FPD-Link II chipset and uses an embedded-clock, transparent serial protocol with defined receiver thresholds. A board-level replacement must match the package, pin assignment, lane count, data rate, protocol framing, clock-recovery behavior, supply requirements, and termination arrangement. Verify the exact ordering suffix and manufacturer documentation rather than inferring interchangeability from distributor descriptions.
コンプライアンス情報
The verified DigiKey and manufacturer ordering information identifies a lead-free NOPB ordering form and reports 8 kV HBM ESD tolerance. RoHS, REACH, halogen-free, conflict-minerals, and exact-MPN AEC-Q100 status were not explicitly supplied.
