DS90CF386SLC - 85MHz 24-Bit LVDS FPD Receiver | TI
部品番号: DS90CF386SLC ✓ 生産中DS90CF386SLC 概要
A flat panel display link receiver is an interface IC that converts a serialized differential display signal into parallel CMOS data for downstream display or timing circuitry. In the broader electronic-component hierarchy, the DS90CF386 belongs to interface ICs, specifically the LVDS receiver class used alongside flat panel display transmitters. Its differential input architecture is intended to improve noise immunity while supporting compact, high-speed connections between display controller and panel electronics.
The primary identified features are an 85 MHz maximum link rate, 24-bit color data capability, a 3.3 V supply, and EIA-644/TIA-644 signaling support. The device also operates in 24-bit mode for flat panel display links. An identified comparison listing reports a 2.38 Gbps data rate for the DS90CF386 family, representing the aggregate signaling capability associated with multiple differential data lanes rather than the per-pixel clock rate.
The DS90CF386 family supports both 24-bit and 18-bit flat panel display operation. Its 64-pin NFBGA option uses a 0.8 mm fine ball pitch and occupies 44 percent less PCB area than the family's 56-pin TSSOP package. This makes the NFBGA implementation particularly useful when display electronics require a compact receiver footprint, although ball-grid-array assembly requires appropriate inspection and rework capability.
Typical applications include digital flat panel display interfaces, LCD controller backplanes, industrial panel displays, commercial display controllers, and embedded display systems using LVDS links. The receiver is most appropriate when the transmitter, cable or PCB channel, connector, and panel electronics have already been designed around EIA-644/TIA-644 LVDS signaling and an 85 MHz pixel-clock requirement.
PCB design should preserve controlled-impedance LVDS routing, provide an uninterrupted reference plane beneath the pair, and place receiver bypass capacitance close to the supply pins. Signal-pair geometry should remain symmetrical, with matched routing through connectors and test points. Because the NFBGA package has fine-pitch balls, assembly process capability, solder-mask design, and board-side thermal and manufacturing requirements should be reviewed before committing the footprint.
This page combines the device identity, package distinctions, interface applications, replacement constraints, and practical PCB considerations needed to evaluate DS90CF386SLC. It also distinguishes the compact NFBGA implementation from package variants that cannot be substituted on an existing board without footprint and pin-assignment changes.
ドロップイン代替品: DS90CF386SLC — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
この製品に利用可能なドロップイン代替品はありません。
代替品をリクエストDS90CF386SLC 仕様
| Product Type | 3.3 V LVDS flat panel display link receiver |
| Supported Color Data Width | 24 bits |
| Maximum Pixel Clock | 85 MHz |
| Family Data Rate | 2.38 Gbps |
| 電源電圧 | 3.3 V |
| LVDS Standard | EIA-644 and TIA-644 |
| 動作温度 | -10 C to +70 C |
| パッケージ | 64-pin NFBGA (NZC) |
| Ball Pitch | 0.8 mm |
| PCB Footprint Reduction | 44% versus the 56-pin TSSOP package |
| ピン数 | 64 pins |
| 実装タイプ | Surface mount |
| Logic Family | LVDS receiver |
| Supported Display Modes | 24-bit and 18-bit flat panel display links |
| Temperature Grade | Commercial grade |
DS90CF386SLC 64-pin nfbga (nzc) ピン配置ガイド
DS90CF386SLC (64-pin nfbga (nzc) パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: DS90CF386SLC.
詳細は データシート をご参照ください。
主な用途
DS90CF386SLC の用途: 6 件s: 24-Bit LCD Flat Panel Display, Industrial Panel Display Interface, Commercial Monitor Controller, Embedded Human-Machine Interface, Digital Signage Display, Compact Display Controller Electronics.
24-Bit LCD Flat Panel Display
The DS90CF386SLC fits a 24-bit LCD flat panel display link because it is specified as a 3.3 V LVDS receiver with an 85 MHz maximum pixel clock. It can receive differential data from a compatible EIA-644/TIA-644 transmitter and deliver parallel digital data to the panel controller. The 64-pin NFBGA (NZC) package also helps reduce board area by 44 percent relative to the family’s 56-pin TSSOP option. Board routing must preserve controlled-impedance differential pairs and a continuous reference plane to maintain LVDS signal quality.
Industrial Panel Display Interface
The DS90CF386SLC is suitable for industrial panel interfaces that use an 85 MHz-or-lower LVDS display channel and operate within the specified -10 C to +70 C range. Differential signaling improves noise immunity in industrial equipment where display cables may pass near motors, switching supplies, or digital power stages. The receiver integrates the link endpoint function, while the compact 0.8 mm-pitch NFBGA preserves PCB area. Its assembly process should be checked against the fine ball pitch, and the display controller and panel must use compatible LVDS timing and data width.
Commercial Monitor Controller
A commercial display controller can use the DS90CF386SLC when the internal display link is a 3.3 V LVDS connection supporting 24-bit color data up to an 85 MHz pixel clock. The receiver supports the EIA-644 and TIA-644 signaling conventions associated with high-speed flat panel links, allowing a compatible transmitter to drive the panel across a compact channel. The NFBGA implementation limits board area, but assembly yield, inspection, rework, and connector-launch geometry remain important layout decisions for a high-volume monitor design.
Embedded Human-Machine Interface
The DS90CF386SLC is appropriate for embedded HMIs that receive color display data from a local controller over LVDS. Its 24-bit mode provides full-color data capability, while the 85 MHz clock limit should be checked against the panel’s native timing, including reduced blanking intervals if used. The compact NFBGA footprint helps when the display electronics compete for board space, but the design must provide uninterrupted reference planes, symmetrical differential routing, and a connector or cable transition whose impedance matches the PCB channel.
Digital Signage Display
Digital signage systems can use the DS90CF386SLC as the receiving endpoint for an 85 MHz LVDS link carrying 24-bit display information. The 3.3 V supply is compatible with contemporary panel-controller logic, and differential transmission helps maintain signal integrity when the controller and display are separated by a cable or board-to-board connection. For long cable runs or unusual grounding conditions, validate the complete transmitter, cable, connector, receiver, and panel channel rather than relying on receiver specifications alone. The fine-pitch NFBGA assembly must also be compatible with the product’s manufacturing process.
Compact Display Controller Electronics
The DS90CF386SLC fits compact display-controller electronics where board area is limited but an LVDS receiver is required. Its 64-pin NFBGA (NZC) implementation uses 0.8 mm ball pitch and offers a documented 44 percent footprint reduction relative to the 56-pin TSSOP package. The device handles the high-speed differential receive stage for a 24-bit link up to 85 MHz, leaving the controller responsible for timing, test, and downstream processing. Layout must account for fine-pitch assembly and preserve continuous return paths beneath every LVDS pair.
エンジニアリング参考データ: DS90CF386SLC — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
設計ノート
Route each LVDS differential pair as a controlled-impedance transmission line over a continuous reference plane. Maintain symmetrical spacing and length through the receiver area, avoid stubs, and bring the pairs to the device in the configuration specified by the manufacturer datasheet. Treat connector launches and test points as discontinuities that require impedance review. The 64-pin NFBGA (NZC) also uses a 0.8 mm ball pitch, so escape routing and manufacturing rules should be resolved before schematic release.
Keep the NFBGA land pattern, solder-mask definition, paste apertures, and board finish aligned with the Texas Instruments package drawing and the selected board-assembly process. Fine-pitch ball-grid arrays require adequate thermal-via and assembly capability; verify inspection and rework procedures rather than assuming that a drawing made for TSSOP will work. Because the manufacturer documentation identifies a 44 percent footprint reduction from the 56-pin TSSOP option, preserve the distinction in PCB library entries and assembly drawings.
Do not substitute DS90CF386SLCX for DS90CF386SLC without redesigning the board. The ordering codes identify different package implementations, so their land patterns and ball assignments cannot be assumed identical. Likewise, DS90CF386SLC/NOPB is the same target device rather than a separate drop-in alternative. Before substitution, verify the 64-pin NFBGA footprint, all signal assignments, supply tolerance, LVDS timing, operating temperature, and the manufacturer’s complete pin-description table.
Place receiver bypass components close to the appropriate 3.3 V supply and ground balls, and keep the return-current path continuous beneath the package. LVDS signaling reduces common-mode noise, but poor reference-plane discontinuities or long supply loops can still degrade receiver performance. Keep the display-link channel away from noisy power-conversion loops and maintain isolation from external cables where the system architecture permits. Validate conducted and radiated emissions at the product level because board layout and cable shielding influence final compliance.
コンプライアンス情報
The Texas Instruments product material and the identified DS90CF386SLC ordering option do not state the requested compliance attributes. No environmental or automotive qualification is inferred from the commercial -10 C to +70 C temperature range.
