DS90LV031TM - Quad 400 Mbps LVDS Driver | Texas Instruments
部品番号: DS90LV031TM ✓ 生産中DS90LV031TM 概要
An LVDS differential line driver is an interface IC that converts single-ended CMOS logic into a pair of complementary low-voltage signals. The receiver detects the voltage difference between those signals, allowing simultaneous noise rejection, low EMI, and reliable data transfer over balanced interconnects. Within the broader hierarchy, DS90LV031TM is a line driver within interface ICs, implemented as a low-power CMOS differential signaling device.
Key features include four CMOS-to-LVDS driver channels, operation above 400 Mbps, LVTTL or LVCMOS input compatibility, and differential output voltage of approximately 350 mV. Common enables allow the outputs to be controlled together, which supports system-level power management and controlled output states. The low-power architecture is intended for high-speed point-to-point communication systems requiring more efficient alternatives to older high-power pseudo-ECL interface devices.
The DS90LV031TM translates four LVCMOS or LVTTL data streams into four balanced LVDS pairs. Differential signaling reduces sensitivity to common-mode noise compared with single-ended transmission, while the approximately 350 mV output amplitude helps control EMI and allows reliable communication over suitable cables or controlled-impedance PCB traces. Its high data-rate capability makes it relevant to clock distribution, parallel data transfer, industrial links, and test equipment.
Typical applications include high-speed backplane links, point-to-point industrial data transfer, parallel-to-serial interface bridges, video or control-data transport, and clock distribution. When used with the companion DS90LV032A receiver, the device provides a complete LVDS transmit and receive path over balanced interconnects.
PCB implementation should preserve differential pair symmetry, provide a continuous return path, and place decoupling close to the supply pins. The 16-pin SOIC package should be oriented according to the manufacturer pinout, with enable and ground connections handled before high-speed signal routing. Exact pin names, supply limits, output timing limits, and termination guidance must be confirmed in the manufacturer datasheet before release to production.
This product page combines verified distributor availability and pricing with manufacturer-family information, cross-reference results, package details, and practical guidance for evaluating the DS90LV031TM as a drop-in LVDS line-driver choice.
ドロップイン代替品: DS90LV031TM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
DS90LV031ATM/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90LV031BTMX
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90LV031ATMX
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90LV031BTM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90LV031A
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DS90LV031TM 仕様
| Product Type | Quad CMOS differential line driver |
| Number of Drivers | 4 channels |
| Maximum Data Rate | Greater than 400 Mbps |
| 最大クロック周波数 | Greater than 200 MHz |
| Input Logic Compatibility | LVTTL or LVCMOS |
| Differential Output Voltage | Approximately 350 mV |
| Signaling Technology | Low-Voltage Differential Signaling (LVDS) |
| Power Dissipation | Ultra-low power dissipation |
| ピン数 | 16 pins |
| パッケージ | 16-pin SOIC (16-SOP) |
| Terminal Form | Gull wing |
| Package Shape | Rectangular |
| Temperature Grade | Industrial |
DS90LV031TM ピン構成
| ピン 1 | EN — Output enable input |
| ピン 2 | EN* — Complementary output enable input |
| ピン 3 | A1 — Differential output for channel 1 |
| ピン 4 | A2 — Differential output for channel 2 |
| ピン 5 | GND — Ground connection |
| ピン 6 | A3 — Differential output for channel 3 |
| ピン 7 | A4 — Differential output for channel 4 |
| ピン 8 | GND — Ground connection |
| ピン 9 | VCC — Positive power supply connection |
| ピン 10 | GND — Ground connection |
| ピン 11 | B4 — Complementary differential output for channel 4 |
| ピン 12 | B3 — Complementary differential output for channel 3 |
| ピン 13 | GND — Ground connection |
| ピン 14 | B2 — Complementary differential output for channel 2 |
| ピン 15 | B1 — Complementary differential output for channel 1 |
| ピン 16 | VCC — Positive power supply connection |
主な用途
DS90LV031TM の用途: 6 件s: High-Speed Point-to-Point Data Links, Industrial Communication Interfaces, Clock Distribution, Parallel Data Transfer, Video Interface Links, Test and Measurement Equipment.
High-Speed Point-to-Point Data Links
The DS90LV031TM is suitable for balanced point-to-point links because its four CMOS differential drivers support data rates in excess of 400 Mbps and generate approximately 350 mV LVDS signals. Each channel can carry a separate clock or data stream over controlled PCB traces or suitable cable. Using complementary differential outputs reduces sensitivity to common-mode noise compared with single-ended transmission. The design should preserve pair symmetry, maintain a continuous ground reference, and verify receiver thresholds, insertion loss, and timing margins at the intended data rate.
おすすめ
Industrial Communication Interfaces
The DS90LV031TM can support industrial communication equipment that transfers several low-voltage digital streams over balanced interconnects. Its quad-driver arrangement reduces the number of separate line-driver packages needed when multiple channels leave one controller or fieldbus interface. Operation above 400 Mbps provides margin for high-speed data movement, while LVDS differential signaling helps limit EMI. Industrial qualification still depends on the confirmed temperature grade, isolation architecture, cable characteristics, surge protection, and grounding strategy of the complete system.
おすすめ
Clock Distribution
The four independent outputs of the DS90LV031TM allow a system to distribute multiple related clock signals over short, balanced connections. Its CMOS-compatible inputs make it suitable for clocks originating in digital controllers, while the approximately 350 mV differential output provides a standard LVDS interface for compatible receivers. Four channels can support related clock groups without occupying four separate driver packages. Timing engineers should verify output jitter, skew, duty-cycle distortion, maximum data rate, and receiver threshold margin because those detailed values were not present in the verified excerpts.
おすすめ
Parallel Data Transfer
The DS90LV031TM fits parallel data-transfer blocks requiring four differential channels from a CMOS or LVTTL source. It can convert four single-ended lanes into balanced LVDS pairs for transmission to a remote receiver, reducing sensitivity to noise coupled into the interconnect. Data rates above 400 Mbps support demanding internal links and short-distance board or rack connections. The implementation must use matched trace geometry, suitable terminations at the receiver, and an equal number of tightly coupled differential pairs to avoid skew between channels.
おすすめ
Video Interface Links
The DS90LV031TM can transmit low-voltage digital video-control or related data signals where balanced lines are needed to control EMI and reject common-mode noise. Its four-driver configuration supports several auxiliary or data channels alongside system control functions, and its greater-than-400-Mbps capability is appropriate for high-speed point-to-point paths. A complete video interface still requires the appropriate pixel-clock, data-lane, and blanking-control architecture. Designers should use controlled-impedance routing and confirm that the selected receiver and cable support the intended video timing.
おすすめ
Test and Measurement Equipment
The DS90LV031TM can provide four low-amplitude differential outputs for test and measurement equipment that distributes control, trigger, or data signals to remote modules. LVDS signaling can improve noise immunity in cabinets and bench systems where cables may pick up interference. The 400 Mbps-capable quad architecture allows related channels to share one driver package while maintaining a common technology. For instrumentation, engineers should evaluate output timing, channel-to-channel skew, reference-clock quality, cable loss, receiver input threshold, and connector transitions before treating the link as a precision measurement path.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DS90LV031TM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DS90LV031ATM/NOPB | DS90LV031BTMX | DS90LV031ATMX | DS90LV031BTM | DS90LV031A |
|---|---|---|---|---|---|---|
| Package | SOIC-16 | SOIC-16 | SOIC-16 | SOIC-16 | SOIC-16 | SOIC-16 |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Driver Configuration | Quad differential driver | Quad differential driver | Quad differential driver | Quad differential driver | Quad differential driver | Quad differential driver |
| Maximum Data Rate | Greater than 400 Mbps | Greater than 400 Mbps | Greater than 400 Mbps | Greater than 400 Mbps | Greater than 400 Mbps | Greater than 400 Mbps |
| Maximum Clock Frequency | Greater than 200 MHz | Greater than 200 MHz | Greater than 200 MHz | Greater than 200 MHz | Greater than 200 MHz | Greater than 200 MHz |
| Input Compatibility | LVTTL or LVCMOS | LVTTL or LVCMOS | LVTTL or LVCMOS | LVTTL or LVCMOS | LVTTL or LVCMOS | LVTTL or LVCMOS |
| Differential Output Voltage | Approximately 350 mV | Approximately 350 mV | Approximately 350 mV | Approximately 350 mV | Approximately 350 mV | Approximately 350 mV |
| Power Architecture | Ultra-low-power CMOS | Ultra-low-power CMOS | Ultra-low-power CMOS | Ultra-low-power CMOS | Ultra-low-power CMOS | Ultra-low-power CMOS |
主な差別化要因
- Documented identical primary performance to the closest ordering-code alternative （vs DS90LV031ATM/NOPB)
- Quad-channel integration reduces package count （vs Single-channel LVDS driver alternatives)
- High-speed LVDS operation in a standard SOIC footprint （vs DS90LV031BTMX)
設計ノート
Route each LVDS channel as a tightly coupled differential pair with symmetric geometry, matched length where channel-to-channel skew matters, and a continuous reference plane. Avoid splitting the ground reference beneath a pair, adding test pads asymmetrically, or introducing unnecessary stubs. For cable transitions, use a controlled-impedance board region and place any required termination at the receiver end according to the receiver and interconnect guidance in the manufacturer datasheet.
Place the device's supply decoupling close to the VCC pins and connect the GND pins to a low-impedance ground plane. The verified excerpts do not provide the capacitor values, permitted ESR, supply range, or input-current limits, so those values must not be guessed. Before release, verify the actual supply voltage, decoupling network, startup behavior, and whether the enable pins are compatible with the host logic levels in the system.
Do not treat a similar ordering code as automatically interchangeable without checking its suffix. DS90LV031ATM/NOPB has a documented identical-performance comparison with DS90LV031TM, whereas the other listed family variants require review of their exact ordering terms. Confirm pinout, temperature grade, supply limits, output timing, package suffix, reel configuration, and lifecycle status. The verified excerpts do not provide the exact numeric differences for every variant.
Validate the complete transmit-to-receive path with realistic cables, PCB traces, connectors, and loading rather than relying only on the greater-than-400-Mbps headline rate. At that rate, loss, reflections, connector transitions, and skew can materially affect eye opening and timing margin. Use the companion DS90LV032A family or another compatible LVDS receiver for reference testing, and confirm the receiver's threshold, termination, jitter, and propagation-delay requirements.
コンプライアンス情報
The verified excerpts do not state RoHS, REACH, lead-free, halogen-free, or conflict-minerals status. The part is an industrial-temperature interface IC, and no AEC-Q100 qualification claim was provided.
