DSPIC33FJ06GS102A-I/SP - 16-bit DSC 40 MIPS 6KB | Microchip
部品番号: DSPIC33FJ06GS102A-I/SP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $5.48 | $5.48 |
| 10 | $4.95 | $49.50 |
| 100 | $4.42 | $442.00 |
| 500 | $3.98 | $1,990.00 |
| 1,000 | $3.6 | $3,600.00 |
DSPIC33FJ06GS102A-I/SP 概要
A digital signal controller combines the compute throughput of a DSP core with the peripheral set and ease of use of a microcontroller. Within the power-management IC hierarchy, the dsPIC33FJ06GS102A sits in the SMPS-focused GS subfamily: it integrates a high-speed PWM module, a high-speed 10-bit ADC, and analog comparators specifically architected for closed-loop digital switch-mode power conversion.
Key features include a 16-bit dsPIC33F core executing at 40 MIPS from a 3.0V to 3.6V supply, on-chip connectivity peripherals (I2C, SPI, UART/USART with IrDA and LIN support), brown-out detect/reset, and dual programmable PGEC/PGED ICSP programming channel pairs for in-circuit debugging. The 24-bit instruction word with DSP multiply-accumulate and barrel shifter accelerates control-loop mathematics such as PID and PFC compensation.
The GS architecture was purpose-built for digital power: the high-resolution PWM supports complementary outputs, dead-time insertion, and fault protection, while the fast ADC can sample at converter-switching frequency with simultaneous or sequential channel scanning, enabling multi-loop control in a single controller.
Typical applications include AC-to-DC converters, DC-to-DC converters, power factor correction (PFC) stages, uninterruptible power supplies, and battery chargers. The 28-pin SPDIP package also makes it convenient for prototyping and low-volume industrial control boards.
Design consideration: the device operates at 3.3V nominal (3.0V to 3.6V), so level shifting is required when interfacing with 5V legacy logic; use the paired PGECx/PGEDx channel for ICSP.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, with pricing references as of 2026-09-26.
ドロップイン代替品: DSPIC33FJ06GS102A-I/SP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ06GS102A-I/SP （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Supply Voltage, Core Architecture, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ06GS102-I/SP
✅ ドロップイン✓ 在庫あり
$1.6 / 個
データシートを見る →DSPIC33FJ06GS102A-E/SP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.38 / 個
データシートを見る →DSPIC33FJ06GS101-I/SP
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ06GS101-E/P
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.05 / 個
データシートを見る →DSPIC33FJ06GS202A-I/SP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
価格はお問い合わせください
データシートを見る →DSPIC33FJ06GS102A-I/SP 最大定格＆電気的特性
| Core Processor | dsPIC33F |
| Core Size | 16-bit |
| Speed | 40 MIPS |
| Program Memory Size | 6 KB (2K x 24) |
| Program Memory Type | Flash |
| RAM Size | 256 bytes |
| 電源電圧 | 3.0 V to 3.6 V (3.3 V nominal) |
| 動作温度 | -40C to +85C (TA) |
| パッケージ | 28-SPDIP (0.300 in, 7.62 mm) |
| 実装タイプ | Through Hole |
| Connectivity | I2C, SPI, UART/USART, IrDA, LIN |
| Peripherals | Brown-out Detect/Reset, High-Speed PWM, ADC, Comparators |
| Number of Timers | 2 |
| Instruction Word Width | 24-bit |
| データバス幅 | 16-bit |
| Packaging | Tube |
| Application Focus | Digital Switch-Mode Power Supplies (SMPS) |
DSPIC33FJ06GS102A-I/SP ピン構成
| ピン 1 | MCLR — Master clear reset (active low), programming voltage input |
| ピン 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / ADC positive reference / change notification / port B bit 0 |
| ピン 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / ADC negative reference / change notification / port B bit 1 |
| ピン 4 | PGED1/EMUD1/AN2/C1IN-/RP0/CN4/RB2 — ICSP data channel 1 / analog input 2 / comparator 1 inverting input / RP0 / port B bit 2 |
| ピン 5 | PGEC1/EMUC1/AN3/C1IN+/RP1/CN5/RB3 — ICSP clock channel 1 / analog input 3 / comparator 1 non-inverting input / RP1 / port B bit 3 |
| ピン 6 | PGED2/AN4/C2IN-/RP2/CN6/RB4 — ICSP data channel 2 / analog input 4 / comparator 2 inverting input / RP2 / port B bit 4 |
| ピン 7 | PGEC2/AN5/C2IN+/RP3/CN7/RB5 — ICSP clock channel 2 / analog input 5 / comparator 2 non-inverting input / RP3 / port B bit 5 |
| ピン 8 | VSS — Ground reference |
| ピン 9 | OSC1/CLKI/RC12 — Crystal oscillator input / external clock input / port C bit 12 |
| ピン 10 | OSC2/CLKO/RC15 — Crystal oscillator output / clock output / port C bit 15 |
| ピン 11 | VDD — Positive supply (3.0V to 3.6V) |
| ピン 12 | RP4/CN1/RB6 — Remappable peripheral pin RP4 / change notification / port B bit 6 |
| ピン 13 | RP5/CN0/RB7 — Remappable peripheral pin RP5 / change notification / port B bit 7 |
| ピン 14 | VSS — Ground reference |
| ピン 15 | RP6/C8/RB8 — Remappable peripheral pin RP6 / comparator output 8 / port B bit 8 |
| ピン 16 | RP7/C9/RB9 — Remappable peripheral pin RP7 / comparator output 9 / port B bit 9 |
| ピン 17 | RP8/CN8/RB10 — Remappable peripheral pin RP8 / change notification / port B bit 10 |
| ピン 18 | RP9/CN9/RB11 — Remappable peripheral pin RP9 / change notification / port B bit 11 |
| ピン 19 | RP10/PWM1L/RB12 — Remappable pin / PWM1 low-side output / port B bit 12 |
| ピン 20 | RP11/PWM1H/RB13 — Remappable pin / PWM1 high-side output / port B bit 13 |
| ピン 21 | RP12/PWM2L/RB14 — Remappable pin / PWM2 low-side output / port B bit 14 |
| ピン 22 | RP13/PWM2H/RB15 — Remappable pin / PWM2 high-side output / port B bit 15 |
| ピン 23 | VDD — Positive supply (3.0V to 3.6V) |
| ピン 24 | RP14/FLTA/RC13 — Remappable pin / PWM fault input A / port C bit 13 |
| ピン 25 | RP15/SOSCI/CN1/RC13 — Remappable pin / secondary oscillator input / change notification |
| ピン 26 | SOSCO/T1CK/CN0/RA4 — Secondary oscillator output / Timer1 external clock / port A bit 4 |
| ピン 27 | AVDD — Analog positive supply |
| ピン 28 | AVSS — Analog ground |
主な用途
DSPIC33FJ06GS102A-I/SP の用途: 6 件s: AC-to-DC Converters, Power Factor Correction (PFC), DC-to-DC Converters, Uninterruptible Power Supplies (UPS), Battery Chargers, Prototyping and Industrial Control Boards.
AC-to-DC Converters
The DSPIC33FJ06GS102A-I/SP fits offline AC-to-DC converter control because its high-speed PWM, fast 10-bit ADC, and analog comparators were co-designed for closed-loop switch-mode regulation. The 40 MIPS 16-bit core executes voltage- and current-loop compensation (PID or 3p3z) well within a 100-500 kHz switching period, while the PWM module provides complementary outputs with programmable dead-time and cycle-by-cycle current limiting via the comparators. Placed as the sole controller driving the power stage gate drivers, it replaces multiple analog control ICs, and firmware enables soft-start, burst mode, and fault logging. Trade-off: firmware development effort replaces fixed analog behavior, so use the Microchip digital power reference designs as a starting codebase.
おすすめ
Power Factor Correction (PFC)
For average-current-mode PFC in boost or interleaved-boost topologies, the DSPIC33FJ06GS102A-I/SP samples input voltage, inductor current, and bus voltage through its high-speed ADC synchronized to the PWM period, then updates duty cycle each switching cycle at 40 MIPS. Microchip's Interleaved PFC reference design based on this controller family operates from universal AC input and delivers up to 350 W of regulated high-voltage DC output, validating the architecture. The ADC-to-PWM synchronization minimizes control latency and switching-noise-induced sampling errors. Design consideration: budget the 6 KB Flash carefully - a full PFC stack with housekeeping and protection typically consumes 4-5 KB, leaving modest headroom.
おすすめ
DC-to-DC Converters
In isolated and non-isolated DC-to-DC converters (buck, boost, flyback, LLC), the DSPIC33FJ06GS102A-I/SP provides the high-resolution, high-speed PWM needed for fixed-frequency control with dead-time insertion, plus comparators for cycle-by-cycle overcurrent protection that react without CPU intervention. Its 3.0-3.6V supply and -40C to +85C industrial rating match telecom and industrial auxiliary power rails. A typical use places the controller between a feedback divider and a gate-driver IC such as a MOSFET driver, updating duty at each ADC interrupt; the 40 MIPS core keeps loop-computation latency to a small fraction of a 100 kHz period. The brown-out detect/reset peripheral guards against undervoltage misbehavior.
おすすめ
Uninterruptible Power Supplies (UPS)
Line-interactive and double-conversion UPS control requires simultaneous management of an inverter, a charger, and transfer logic - a fit for the DSPIC33FJ06GS102A-I/SP's synchronized multi-channel ADC and complementary PWM outputs. The 40 MIPS core runs inverter sinusoidal regulation and battery-charge state algorithms concurrently, while the UART supports status communication to a host or LCD. Microchip explicitly lists UPS among the GS subfamily's target applications. For a basic offline UPS, the 6 KB Flash suffices; for grid-tie or advanced battery management, migrate to the pin-compatible DSPIC33FJ06GS202A-I/SP with 12 KB Flash on the same footprint. Fault comparators provide hardware-level protection independent of software state.
おすすめ
Battery Chargers
Smart battery chargers (Li-ion CC/CV, lead-acid multi-stage) benefit from the DSPIC33FJ06GS102A-I/SP's combination of precise ADC sensing, PWM charge control, and communication peripherals. The fast ADC monitors battery voltage and current each switching cycle for accurate CC/CV regulation, while the PWM drives the buck charger power stage with current-mode control implemented in firmware. UART or I2C connects to gas-gauge ICs or host systems for charge-status reporting, and the comparators implement hardware overcurrent cutoff. The 256 bytes of RAM comfortably hold a charging state machine. Note the 3.3V logic domain: battery-sense dividers and cell-balancing front ends must be scaled to within the ADC input range.
おすすめ
Prototyping and Industrial Control Boards
The 28-pin SPDIP through-hole package makes the DSPIC33FJ06GS102A-I/SP exceptionally convenient for breadboarding, test fixtures, and low-volume industrial equipment where hand soldering and socketing matter. Despite the SMPS-oriented peripheral set, it serves as a general 40 MIPS 16-bit controller with I2C, SPI, UART, IrDA, and LIN connectivity, two timers, and brown-out protection - suitable for sensor aggregation, small motor drives, and automation nodes. The dual PGEC/PGED ICSP pairs allow debugging with PICkit tools without removing the device from the socket. Design consideration: the 0.300-inch 7.62 mm DIP footprint eases rework in evolving prototypes compared to SOIC/QFN equivalents.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ06GS102A-I/SP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ06GS102-I/SP | DSPIC33FJ06GS102A-E/SP | DSPIC33FJ06GS101-I/SP | DSPIC33FJ06GS202A-I/SP |
|---|---|---|---|---|---|
| Package | 28-SPDIP (0.300 in, 7.62 mm) | 28-SPDIP - same | 28-SPDIP - same | 28-SPDIP - same | 28-SPDIP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Program Memory | 6 KB | 6 KB | 6 KB | 3 KB | 12 KB |
| RAM | 256 bytes | 256 bytes | 256 bytes | 128 bytes | 512 bytes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Digital Power Peripherals | High-Speed PWM, ADC, Comparators | Same set | Same set | Same set | Same set |
| Connectivity | I2C, SPI, UART/USART, IrDA, LIN | I2C, SPI, UART/USART, IrDA, LIN | I2C, SPI, UART/USART, IrDA, LIN | I2C, SPI, UART/USART, IrDA, LIN | I2C, SPI, UART/USART, IrDA, LIN |
主な差別化要因
- Full 6 KB Flash for complete digital power firmware （vs DSPIC33FJ06GS101-I/SP)
- Extended temperature option on identical pinout （vs DSPIC33FJ06GS102A-E/SP)
- Cost-optimized for single-converter designs （vs DSPIC33FJ06GS202A-I/SP)
設計ノート
Supply the dsPIC33FJ06GS102A-I/SP from a clean 3.3V rail (3.0-3.6V absolute range) and separate AVDD from digital VDD via an RC or ferrite filter so ADC accuracy is not degraded by PWM switching noise - critical in the SMPS applications this part targets. Decouple each VDD/VSS pair with 0.1 uF ceramics placed within a few millimeters of the pins, plus a 4.7-10 uF bulk capacitor. Estimated: at 40 MIPS the core draw is in the tens-of-mA class; verify against datasheet typical ICC curves for your clock configuration.
Keep the PWM output traces away from the ADC input traces, and route the comparator/PWM fault line (FLTA) short and directly to the shutdown transistor since it provides cycle-by-cycle hardware protection. On two-layer boards, pour ground under the controller and connect AVSS/VSS at a single star point. Because the SPDIP package is through-hole, long leads on protoboards add inductance - on production PCBs, place the controller close to the gate drivers rather than the power stage to minimize gate-loop inductance.
ICSP requires a matched PGECx/PGEDx pair: per Microchip's programming guidance, if PGEC2 carries ICSPCLK, ICSPDAT must be on PGED2 - mixing pairs across channels fails programming. Also, do not exceed 3.6V on any digital input when interfacing 5V logic; use level shifters. Finally, the GS family's ADC and PWM timing registers differ from dsPIC33EP parts, so code ported between subfamilies must be re-verified rather than assumed compatible.
コンプライアンス情報
RoHS compliant and lead-free per Microchip product page and distributor listings. Halogen-free and conflict-minerals declarations should be confirmed against the latest Microchip material declaration sheet for the specific date code.
