DSPIC33FJ128GP706A-E/MR - 16-Bit DSC, 40 MIPS, 128KB Flash | Microchip
部品番号: DSPIC33FJ128GP706A-E/MR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.78 | $57.80 |
| 100 | $5.14 | $514.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.2 | $4,200.00 |
DSPIC33FJ128GP706A-E/MR 概要
A digital signal controller combines the computational core of a microcontroller with the multiply-accumulate (MAC) engine of a digital signal processor. In the product hierarchy, the dsPIC33FJ sits between general-purpose MCUs (like the PIC18) and dedicated DSPs, offering C-friendly 16-bit architecture plus single-cycle MAC, hardware division and DSP instructions - all within one power-managed semiconductor device suited for mixed control-plus-signal-processing workloads.
Key features include 40 MIPS execution at 3.3V operation, 128 KB Flash with self-programming capability, 16 KB SRAM, dual internal bus architecture for simultaneous fetch operations, an AEC-Q100 automotive-grade qualified die, and extended (-E) temperature operation to +125C. Multiple PGECx/PGEDx pairs support in-circuit serial programming (ICSP) and debugging, with any pin pair usable as long as clock and data are used as a pair per Microchip documentation.
The dsPIC33FJ architecture integrates a 16-bit modified Harvard core with DSP multiply, 40-bit accumulators and hardware loop support, allowing digital filters and FFTs to execute alongside motor-control and communications tasks without a second chip. Peripherals typical of the GP (general purpose) family variant include UART, SPI and I2C serial interfaces plus analog and timer resources detailed in the manufacturer datasheet.
Typical applications span motor control and power conversion, digital audio and sensor signal processing, and automotive/industrial control nodes where the -E extended temperature range and AEC-Q100 qualification are decisive selection factors.
When designing with this device, connect ALL VDD and VSS pins and pair PGECx with the matching PGEDx for programming - mixing pairs from different sets is a common bring-up failure.
This page synthesizes distributor pricing, pinout guidance, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: DSPIC33FJ128GP706A-E/MR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ128GP706A-E/MR （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Core Architecture, Flash Program Memory, Packaging.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ128GP706AT-E/MR
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DSPIC33FJ128GP706A-I/MR
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DSPIC33FJ128GP706A-H/MR
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価格はお問い合わせください
データシートを見る →DSPIC33FJ128GP706-E/MR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP706-I/MR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP706A-E/MR 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33FJ |
| Max CPU Speed | 40 MIPS |
| Flash Program Memory | 128 KB (128K x 8) |
| パッケージ | 64-VQFN (9x9 mm), MR suffix |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +125C (E grade) |
| Qualification | AEC-Q100 (Automotive) |
| Family Series | dsPIC 33F |
| Programmability | ICSP via PGECx/PGEDx pairs |
| Lead Free Status | Lead free / RoHS Compliant |
| Product Type | Digital Signal Controller (DSC), 16-Bit MCU/DSP |
| ピン数 | 64 |
| Migration Path | Seamless migration to other DSCs in similar packages |
| Packaging | Tube (per Future Electronics listing) |
DSPIC33FJ128GP706A-E/MR 64-vqfn (9x9 mm), mr suffix ピン配置ガイド
DSPIC33FJ128GP706A-E/MR (64-vqfn (9x9 mm), mr suffix パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ128GP706A-E/MR.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ128GP706A-E/MR の用途: 6 件s: Motor Control and Power Conversion, Digital Audio Signal Processing, Automotive Body and Powertrain-Adjacent Electronics, Industrial Sensor Conditioning and Acquisition, Embedded Control with Real-Time DSP in Test Instruments, Power Supply and Digital Power Management.
Motor Control and Power Conversion
The DSPIC33FJ128GP706A-E/MR fits motor control because its 16-bit DSP core executes at 40 MIPS with single-cycle MAC instructions, sustaining current-loop bandwidths that general-purpose MCUs cannot reach. The dsPIC33F family's motor-control peripherals drive three-phase inverters for BLDC, PMSM and induction machines, while the 128 KB Flash holds field-oriented control firmware plus communications stacks. The -40C to +125C extended rating tolerates drive-enclosure heating near power stages. Because PWM generation and feedback filtering run on the same chip, no external signal processor is needed, reducing BOM cost and board area in industrial drives, servo amplifiers, and power-factor-correction converters. Estimated thermal margin should always be validated against package power dissipation in the datasheet.
おすすめ
Digital Audio Signal Processing
Digital audio pipelines benefit directly from the DSP engine in the DSPIC33FJ128GP706A-E/MR: the 40-bit accumulators and hardware MAC support execute IIR/FIR filters and sample-rate processing at 40 MIPS without accumulator overflow management in software. The GP (general purpose) peripheral variant supplies the serial interfaces needed to move audio sample streams between codecs and the controller. In effects processors, amplifiers with DSP pre-processing, and audio test equipment, the single-chip solution combines control logic, user-interface handling and signal processing. The 128 KB Flash accommodates filter coefficient tables and multiple processing presets. Compared with a separate MCU-plus-DSP two-chip design, this DSC cuts inter-chip latency and simplifies firmware architecture significantly.
おすすめ
Automotive Body and Powertrain-Adjacent Electronics
The AEC-Q100 qualification and -E extended temperature range make the DSPIC33FJ128GP706A-E/MR a natural fit for automotive electronic modules such as sensor nodes, pump and fan controllers, lighting control, and powertrain-adjacent actuators. AEC-Q100 stress testing (per Automotive Electronics Council standards) validates die-level reliability across the automotive temperature cycles, while the 125C ceiling covers modules mounted near heat sources. The 64-pin VQFN's 9x9 mm footprint suits space-constrained ECUs, and ICSP programming allows re-flashing on the production line. Designers should pair the controller with automotive-qualified support components and validate the complete module against the applicable OEM qualification plan beyond the component-level AEC-Q100 certificate.
おすすめ
Industrial Sensor Conditioning and Acquisition
Sensor acquisition chains use the DSP capabilities of the DSPIC33FJ128GP706A-E/MR to run digital filtering, RMS computation and calibration routines in firmware at 40 MIPS, eliminating external analog conditioning complexity. The 128 KB Flash stores multi-point calibration tables and communication protocol stacks (Modbus and similar industrial links) concurrently. The extended -40C to +125C rating permits mounting acquisition boards inside panels, motors, or outdoor enclosures without local heating control. Multiple PGECx/PGEDx ICSP pairs enable field firmware updates through any chosen pair, provided clock and data come from the same set. For vibration, pressure, and temperature sensing nodes where one chip must condition, compute, and communicate, this DSC consolidates the signal chain.
おすすめ
Embedded Control with Real-Time DSP in Test Instruments
Handheld and benchtop instruments need both responsive control (menus, displays, communications) and real-time DSP (filtering, FFT-based analysis) - the DSPIC33FJ128GP706A-E/MR delivers both on one 40 MIPS core. The 16 KB-class SRAM buffers acquisition windows while the DSP engine computes results, and the 64-pin VQFN packages the whole instrument controller into a compact PCB area. Extended temperature operation suits portable instruments used in vehicles and field service. The seamless migration options within the dsPIC33F family, noted by distributors such as Future Electronics, let instrument makers scale Flash and peripherals across product tiers without re-spinning core firmware architecture. Debugging provisions over any PGECx/PGEDx pair accelerate firmware bring-up.
おすすめ
Power Supply and Digital Power Management
Digitally controlled power supplies (server VRMs, telecom rectifiers, solar converters) exploit the DSPIC33FJ128GP706A-E/MR's fast control loops: at 40 MIPS with single-cycle MAC, compensator updates execute well above typical switching-frequency Nyquist needs. Firmware-based control enables adaptive algorithms, telemetry, and PMBus-style communication that fixed analog controllers cannot offer. The +125C junction capability is essential because power-supply environments routinely exceed +85C ambient near magnetics and switches. The 64-pin QFN provides enough GPIO for PWM outputs, current/voltage feedback, fault handling, and housekeeping I/O. Estimated junction rise should be computed from switching-loss-affected peripheral activity using datasheet thermal resistance before finalizing the thermal design.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ128GP706A-E/MR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ128GP706AT-E/MR | DSPIC33FJ128GP706A-I/MR | DSPIC33FJ128GP706A-H/MR | DSPIC33FJ128GP706-I/MR |
|---|---|---|---|---|---|
| Package | 64-VQFN (9x9 mm) | 64-VQFN (9x9 mm) - same | 64-VQFN (9x9 mm) - same | 64-VQFN (9x9 mm) - same | 64-VQFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Max CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| AEC-Q100 Qualified | Yes | Yes (same die) | Yes | Yes | Yes |
| Die Revision | A (revised) | A (revised) | A (revised) | A (revised) | Original (pre-A) |
主な差別化要因
- Extended -40C to +125C temperature range （vs DSPIC33FJ128GP706A-I/MR)
- Revised A-step silicon （vs DSPIC33FJ128GP706-I/MR)
- Tube packaging for prototyping （vs DSPIC33FJ128GP706AT-E/MR)
設計ノート
Connect ALL VDD and VSS pins on the 64-pin QFN - omitting any power pin is the most common cause of ICSP programming failure and erratic operation on the dsPIC33FJ family. Per the NSDSP programming documentation for dsPIC33FJ128GP706A, every power pin must be connected during programming and debugging. Place a 100 nF ceramic decoupling capacitor at each VDD/VSS pin pair with short, direct traces to the ground plane, and use the exposed pad under the VQFN-64 as a low-impedance ground connection with a via array.
When wiring the ICSP header, PGECx and PGEDx must come from the SAME pair - for example PGEC2 with PGED2. Mixing PGEC2 with PGED1 will silently fail programming. The device has multiple clock/data pairs so you can route the header to whichever pair is most convenient for your PCB layout, but never split pairs. Also verify MCLR is pulled up appropriately and that your programmer voltage level matches the dsPIC33FJ 3.3V specification; 5V programmers without level shifting can damage the device.
The -E grade permits +125C operation, but junction temperature is the binding constraint, not ambient. Estimated: junction rise equals power dissipation multiplied by theta-JA from the datasheet; with the QFN exposed pad well soldered to a copper pour, achievable dissipation improves substantially versus a floating pad. For motor-drive and digital-power applications where peripherals switch continuously, compute worst-case dissipation at maximum MIPS and maximum peripheral load, then confirm junction stays below the 125C ceiling with margin. Derive final figures from the manufacturer datasheet thermal tables rather than rule-of-thumb values.
コンプライアンス情報
Lead free / RoHS Compliant per distributor listing (besenchips). AEC-Q100 automotive qualified per DigiKey product listing. REACH and halogen-free status not stated in provided data.
