DSPIC33FJ32MC202-I/SP - 16-bit DSC 40MIPS 32KB Flash | Microchip
部品番号: DSPIC33FJ32MC202-I/SP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.34 | $4.34 |
| 10 | $4.12 | $41.20 |
| 100 | $3.86 | $386.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.25 | $3,250.00 |
DSPIC33FJ32MC202-I/SP 概要
A digital signal controller is a hybrid device that merges the deterministic control flow of a microcontroller (MCU) with the mathematical throughput of a digital signal processor (DSP). Within the power-management hierarchy, the dsPIC33F family sits between basic MCUs and dedicated DSPs, offering a modified Harvard 16-bit architecture with DSP-enhanced instructions (MAC, DSP multiply, barrel shifter) while retaining flash self-programming, interrupt-driven peripherals, and low-cost development tools.
Key features include two PWM generators with independent timebases for motor drive, an 8-channel 10-bit/1.1 Msps ADC, up to two high-speed analog comparators, Peripheral Pin Select (PPS) for flexible digital I/O mapping, 5 timers, an 8-channel DMA controller, and UART, SPI, and I2C serial interfaces. Supply voltage is 3.0V to 3.6V (3.3V nominal).
Architecturally, the dsPIC33F CPU executes most instructions in a single cycle from a 16-bit modified Harvard bus structure, with 40 MIPS sustained performance at 3.3V. Hardware DSP support includes dual fetch, modulo and bit-reversed addressing, and 40-bit accumulators, enabling FOC (field-oriented control) loops for brushless DC and PMSM motors without an external DSP.
Typical applications include sensorless BLDC and ACIM motor control, digital power supplies (LLC, PFC, buck), uninterruptible power supplies, and embedded control systems requiring deterministic PWM timing. The 28-pin SPDIP through-hole package is ideal for prototyping, hobby, education, and low-volume industrial boards.
Design consideration: place a 10 uF low-ESR capacitor on the VCAP/VDDCORE pin; enable the onboard 1.8V core regulator correctly, and provide clean AVDD/AVSS isolation for the ADC to preserve converter accuracy.
This page synthesizes distributor pricing, drop-in same-footprint alternatives, design notes, and FAQ content not consolidated in the manufacturer datasheet.
ドロップイン代替品: DSPIC33FJ32MC202-I/SP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ32MC202-I/SP （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Core Architecture, Mounting Type, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ32MC202-E/SP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.6 / 個
データシートを見る →DSPIC33FJ64MC202-I/SP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$0.13 / 個
データシートを見る →PIC24HJ32MC202-I/SP
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ32MC302-I/SP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.92 / 個
データシートを見る →DSPIC33FJ32GP202-I/SP
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ32MC202-I/SP 最大定格＆電気的特性
| Core Processor | dsPIC33F |
| Core Size | 16-bit |
| Maximum Speed | 40 MIPS (40 MHz) |
| Program Memory Size | 32 KB (11K x 24) Flash |
| RAM Size | 2 KB |
| Supply Voltage Range | 3.0 V to 3.6 V |
| 動作温度 | -40C to +85C |
| ADC Resolution | 10 bit |
| ADC Channels | 8 channels, up to 1.1 Msps |
| PWM Channels | 2 PWM generators with independent timebases |
| Comparators | 2 high-speed comparators |
| Timers | 5 timers |
| DMA Channels | 8-channel DMA |
| Connectivity | UART, SPI, I2C |
| I/O Ports | Up to 21 I/O (Peripheral Pin Select) |
| パッケージ | 28-pin SPDIP (through-hole) |
| 実装タイプ | Through Hole |
| Architecture | Modified Harvard, DSP-enhanced instruction set |
| RoHS ステータス | Compliant (lead-free plastic package) |
DSPIC33FJ32MC202-I/SP ピン構成
| ピン 1 | MCLR — Master clear reset (active low), ICSP programming voltage input |
| ピン 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / ADC positive reference / change notification / port B bit 0 |
| ピン 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / ADC negative reference / change notification / port B bit 1 |
| ピン 4 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI slave select 1 / change notification / port B bit 2 |
| ピン 5 | AN3/INDX/CN5/RB3 — Analog input 3 / QEI index input / change notification / port B bit 3 |
| ピン 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEI phase A / input capture 7 / port B bit 4 |
| ピン 7 | VDD — Positive supply (3.0V to 3.6V) |
| ピン 8 | VSS — Ground reference |
| ピン 9 | OSC1/CLKI — Crystal oscillator input / external clock input |
| ピン 10 | OSC2/CLKO/RC15 — Crystal oscillator output / clock output / port C bit 15 |
| ピン 11 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / QEI phase B / input capture 8 / port B bit 5 |
| ピン 12 | AN6/RB8 — Analog input 6 / port B bit 8 |
| ピン 13 | AN7/RB9 — Analog input 7 / port B bit 9 |
| ピン 14 | VSS — Ground reference |
| ピン 15 | AN9/RB15 — Analog input 9 / port B bit 15 |
| ピン 16 | AN10/RB13 — Analog input 10 / port B bit 13 |
| ピン 17 | AN11/RB12 — Analog input 11 / port B bit 12 |
| ピン 18 | AN12/RB11 — Analog input 12 / port B bit 11 |
| ピン 19 | AN13/RB10 — Analog input 13 / port B bit 10 |
| ピン 20 | VCAP/VDDCORE — Internal core regulator output - connect 10 uF low-ESR capacitor to VSS |
| ピン 21 | PGC/RB6 — Programming clock (ICSP) / port B bit 6 |
| ピン 22 | PGD/RB7 — Programming data (ICSP) / port B bit 7 |
| ピン 23 | RP3/SDO1 — Remappable pin RP3 / SPI1 data out (via PPS) |
| ピン 24 | RP2/SDI1 — Remappable pin RP2 / SPI1 data in (via PPS) |
| ピン 25 | RP13/T1CK — Remappable pin RP13 / Timer1 external clock (via PPS) |
| ピン 26 | RP11/U2RX — Remappable pin RP11 / UART2 receive (via PPS) |
| ピン 27 | AVSS — Analog ground for ADC/comparators |
| ピン 28 | AVDD — Analog supply for ADC/comparators |
主な用途
DSPIC33FJ32MC202-I/SP の用途: 6 件s: Sensorless BLDC / PMSM Motor Control, Digital Power Supplies (LLC, PFC, Buck), Uninterruptible Power Supplies (UPS), Industrial Sensing and Control Nodes, Prototype, Education, and Hobby Projects, Audio Signal Processing and Effects.
Sensorless BLDC / PMSM Motor Control
The DSPIC33FJ32MC202-I/SP fits brushless DC and PMSM control because its two PWM generators with independent timebases produce complementary outputs with hardware dead-time, while the 8-channel 10-bit ADC at up to 1.1 Msps samples phase currents synchronized to PWM triggers for jitter-free field-oriented control. Running at 40 MIPS with hardware DSP multiply-accumulate instructions, the core executes current-loop and speed-loop algorithms with single-cycle MAC operations. The two high-speed comparators connect directly to PWM fault inputs, enabling cycle-by-cycle overcurrent shutdown without software latency. Typical usage pairs the DSC with a three-phase gate driver (e.g., MCP8025-style integrated drivers) and current-sense shunts; the main trade-off is the 3.3V-only supply, requiring logic-level translation to 5V gate drivers.
おすすめ
Digital Power Supplies (LLC, PFC, Buck)
For digitally controlled power conversion, the DSPIC33FJ32MC202-I/SP provides the required timing precision: PWM generators support complementary mode, dead-time insertion, and phase-shifted operation suited to LLC and PFC topologies, while PWM-triggered ADC sampling at up to 1.1 Msps keeps feedback loops deterministic. The 40 MIPS core with DSP instructions implements compensator (PI/PID or 2p2z) math in single-cycle MAC operations, achieving control-loop rates of tens of kHz. High-speed analog comparators give hardware overcurrent protection on a per-cycle basis, independent of firmware. In a typical design the DSC sits between the feedback divider and gate drivers; the key performance consideration is ADC reference stability, so a precision voltage reference such as the MCP1541 is recommended over the raw 3.3V rail.
おすすめ
Uninterruptible Power Supplies (UPS)
The DSPIC33FJ32MC202-I/SP serves UPS control because the application demands simultaneous inverter PWM generation, battery-voltage and current telemetry, and fast fault handling - all delivered by its dual independent-timebase PWM generators, 1.1 Msps ADC, and hardware comparator protection. The 40 MIPS core executes sine-wave reference generation and dual-loop (voltage outer, current inner) regulation with DSP-enhanced math at 16-bit fixed-point precision, while the 8-channel DMA offloads ADC result transfer so the CPU is not stalled by data movement. UART connectivity supports host communication for status and configuration. Design consideration: the -I/SP industrial rating of +85C suits typical UPS enclosures, but forced airflow or derating is required near the inverter heatsink in compact designs.
おすすめ
Industrial Sensing and Control Nodes
In factory automation nodes, the DSPIC33FJ32MC202-I/SP combines general-purpose MCU convenience with DSP-class throughput. Peripheral Pin Select (PPS) lets firmware remap UART, SPI, and I2C functions across RPn pins, which simplifies single-PCB variants for different sensor front-ends. The 8-channel ADC digitizes analog sensor inputs at up to 1.1 Msps for vibration or current signatures, and DMA moves results to RAM without CPU intervention, preserving headroom for 40 MIPS of protocol processing. Two UARTs, SPI, and I2C cover Modbus-RTU, sensor buses, and EEPROM expansion simultaneously. The -40C to +85C industrial rating and 32 KB flash support compact, feature-rich firmware; for higher node counts, the same-footprint 64 KB MC202 variant removes memory ceilings without PCB change.
おすすめ
Prototype, Education, and Hobby Projects
The 28-pin SPDIP through-hole package makes the DSPIC33FJ32MC202-I/SP exceptionally friendly to breadboarding, university labs, and low-volume builds where 0.5 mm-pitch QFN or SSOP packages are impractical. At roughly $4.34 per unit (as of 2026-09-27 at LCSC), it delivers a 40 MIPS 16-bit DSP core, on-chip flash self-programming, and PPS pin flexibility at prototyping-friendly cost. In-circuit serial programming (ICSP) via the MCLR/PGC/PGD pins works with the PICkit 3/4 programmers, and free MPLAB X IDE plus the MPLAB XC16 compiler support the full toolchain at no license cost. Typical learning designs pair the DSC with an LDO regulator and an ICSP header; the main consideration is the strict 3.0V-3.6V supply window compared with 5V-tolerant classic PICs.
おすすめ
Audio Signal Processing and Effects
With a 16-bit modified Harvard core, single-cycle MAC, 40-bit accumulators, and bit-reversed addressing for FFTs, the DSPIC33FJ32MC202-I/SP can implement real-time audio effects, filters, and tone generation at 40 MIPS - sufficient for 48 kHz mono processing with moderate algorithm complexity. The 10-bit/1.1 Msps ADC captures control inputs (pots, sensors) while SPI links to external audio codecs for higher-fidelity conversion, since the on-chip 10-bit ADC is intended for control rather than hi-fi audio. DMA offloads codec data transfer, keeping the core available for IIR/FIR computation. Through-hole SPDIP packaging supports rapid prototyping of guitar pedals and educational DSP demos; for stereo hi-fi applications, an external codec such as the AK4556-style device is the recommended signal path.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ32MC202-I/SP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ32MC202-E/SP | DSPIC33FJ64MC202-I/SP | PIC24HJ32MC202-I/SP | DSPIC33FJ32GP202-I/SP |
|---|---|---|---|---|---|
| Package | 28-pin SPDIP | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Speed | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | PIC24H, 40 MIPS (no DSP instructions) | dsPIC33F, 40 MIPS |
| Flash Program Memory | 32 KB | 32 KB | 64 KB | 32 KB | 32 KB |
| RAM | 2 KB | 2 KB | 2 KB | 2 KB | 2 KB |
| Operating Temperature | -40C to +85C | -40C to +125C (extended) | -40C to +85C | -40C to +85C | -40C to +85C |
| PWM Peripherals | 2 high-speed PWM generators, independent timebases | 2 high-speed PWM generators | 2 high-speed PWM generators | 2 high-speed PWM generators | Standard output-compare PWM (not high-speed MC type) |
| Lifecycle Status | Active | Active | Active | Active | Active |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
主な差別化要因
- Hardware DSP engine for motor control math （vs PIC24HJ32MC202-I/SP)
- Double the flash in the same footprint （vs DSPIC33FJ64MC202-I/SP)
- Extended temperature capability without redesign （vs DSPIC33FJ32MC202-E/SP)
設計ノート
The DSPIC33FJ32MC202-I/SP uses an internal 1.8V core regulator fed from the 3.3V rail; pin 20 (VCAP/VDDCORE) MUST have a low-ESR capacitor (Microchip recommends approximately 10 uF ceramic) directly to VSS. Omitting or undersizing this capacitor causes brown-out resets and erratic core operation. Keep VDD within 3.0V-3.6V at all times; the device is not 5V tolerant on any I/O, so 5V signals require level shifting or series resistors per Microchip application guidance.
Decouple each VDD pin (pin 7) with a 0.1 uF ceramic placed within 5 mm of the pin, plus one bulk 4.7 uF-10 uF capacitor per board. Connect AVDD (pin 28) to VDD through a ferrite bead or RC filter and AVSS (pin 27) to a quiet analog ground point to preserve the 10-bit ADC's effective resolution when sampling PWM-synchronized motor currents. On through-hole SPDIP prototypes, use short, direct ground returns for the analog reference path.
Configure the FOSC/FPOR configuration words for the correct oscillator source and the correct PWM pin mapping before first flash - a misconfigured PLL setting can lock out ICSP recovery. Remember that Peripheral Pin Select (PPS) requires unlocking (sequence writes to OSCCON) before remap registers can be changed, and PPS-mapped digital peripherals share pins with analog functions that must be set to digital mode (AD1PCFGL) at startup. Follow Microchip motor-control application notes (e.g., AN1292 family) for sensorless FOC frameworks.
コンプライアンス情報
Package described as lead-free plastic (per distributor datasheet listing); MicrochipDirect confirms conflict minerals program compliance. AEC-Q100 qualification not specified for this industrial (-I) part.
