Altera

EP1K100QC208-2N - ACEX-1K FPGA 4992 LE, 147 IO | Altera

Name: EP1K100QC208-2N - ACEX-1K FPGA 4992 LE, 147 IO | Altera
Brand: Altera
SKU: EP1K100QC208-2N
Price: 16.42 USD
Availability: InStock

部品番号: EP1K100QC208-2N ✗ 生産終了

在庫あり 1〜3営業日以内に発送

2.5 V Vdss 208-PQFP / 208-BFQFP Package -2 Speed

開始価格 $16.42 USD / 個

MOQ: 1 |

価格更新日: 2026-09-06

ボリューム価格

数量	単価	小計
1	$24.33	$24.33
10	$22.16	$221.60
100	$19.72	$1,972.00
500	$17.9	$8,950.00
1,000	$16.42	$16,420.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP1K100QC208-2N 概要

The Intel (Altera) EP1K100QC208-2N is an ACEX 1K family field-programmable gate array with 4,992 logic elements arranged in 624 LABs, 49,152 total RAM bits, and 147 user I/O pins, supplied in a 208-pin PQFP package. It operates from a 2.5V core supply, uses CMOS technology, and supports a 0C to 70C commercial temperature range. The -2 speed grade places it between the faster -1 and slower -3 variants in the same 208-pin footprint.\n\nAn FPGA is an integrated circuit whose logic fabric is configured after manufacturing to implement custom digital hardware. Unlike a fixed-function ASIC or microcontroller, an FPGA consists of programmable lookup tables, flip-flops, routing resources, and embedded memory blocks that together form arbitrary logic circuits. In the power-management and processing hierarchy, this product belongs to programmable logic devices, above simple CPLDs in complexity and below application-specific standard parts in unit-volume cost optimization. For designers needing deterministic, parallel digital logic without wafer fabrication, an FPGA provides a fast path between algorithm and hardware.\n\nKey features of the EP1K100QC208-2N include 4,992 logic elements per the verified family specification, 49,152 RAM bits for on-chip packet buffering and FIFO storage, 624 LABs for distributed control logic, and 147 user I/O pins in a 208-pin PQFP. The device uses a 2.5V core voltage, reducing dynamic power compared with 5V predecessors, while the -2 speed grade supports typical clock rates up to about 250 MHz as reported by listings for this part. Altera's ACEX 1K architecture includes an embedded array suitable for implementing memory and specialized logic functions.\n\nThe internal architecture combines logic array blocks with embedded array blocks for system-on-a-programmable-chip integration. This allows functions such as dual-port RAM, CAM, and DSP storage to reside on-chip, reducing board area and latency. The technology is CMOS 0.22um, and the part is classified as obsolete at end-of-life status in current distributor records. Because ACEX 1K uses SRAM-based configuration, an external boot source such as an EPC configuration device is required to load the bitstream after power-up.\n\nTypical applications include protocol bridging, industrial I/O control, image preprocessing, data acquisition in test instrumentation, and legacy product lifecycle replacement. The 147 I/O count is sufficient for 32/64-bit data paths plus handshaking, and the 49,152 RAM bits support small FIFOs and line buffers. For designs that need parallel throughput rather than sequential processing, the EP1K100QC208-2N can implement several bus converters or custom state machines in a single device.\n\nWhen designing with this component, remember that it is volatile and obsolete. Add an EPC2 or host-processor configuration path, maintain the 2.5V core rail with adequate bulk capacitance, and confirm current stock before committing to a large production run because no modern pin-compatible FPGA replacement exists. For new designs, select a current FPGA family instead of ACEX 1K.\n\nThis page synthesizes distributor pricing, drop-in speed-grade alternatives, architecture notes, and practical configuration guidance not repeated in raw datasheet snippets, giving engineers a compact cross-reference for maintaining legacy ACEX 1K systems.

ドロップイン代替品: EP1K100QC208-2N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP1K100QC208-2N （同一形状・フットプリント） — 相違点: Speed Grade, Process Technology, Package, Family, Configuration Method.

EP1K100QC208-1

Altera

Speed Grade: -1

Process Technology: 0.22 µm

Family: ACEX-1K

比較対象 EP1K100QC208-2N →

EP1K100QC208-1GZ

Intel

Family: ACEX 1K Device Family (2.5 V)

比較対象 EP1K100QC208-2N →

EP1K100QC208-1N

Altera

Speed Grade: -1

Process Technology: 0.22 um CMOS

比較対象 EP1K100QC208-2N →

EP1K100QC208-2

Altera

Process Technology: CMOS

Package: 208-pin PQFP (FQFP, gull-wing)

Family: ACEX-1K

比較対象 EP1K100QC208-2N →

EP1K100QC208-2NGZ

Intel

Speed Grade: -2 (medium speed)

Configuration Method: SRAM (volatile), external EPC series PROM

比較対象 EP1K100QC208-2N →

EP1K100QC208-3

Altera

Speed Grade: -3

Process Technology: 0.22 um CMOS

比較対象 EP1K100QC208-2N →

EP1K100QC208-3N

Altera

比較対象 EP1K100QC208-2N →

EP1K100QI208-02

Altera

Speed Grade: -02 (slowest)

Process Technology: 0.22 µm SRAM

Package: 208-BFQFP (PQFP, gull-wing)

比較対象 EP1K100QC208-2N →

EP1K100QI208-2

Altera

Process Technology: 0.22 umm CMOS SRAM

Package: 208-pin PQFP (BFQFP)

Family: ACEX-1K

比較対象 EP1K100QC208-2N →

EP1K100QI208-2N

Altera

Speed Grade: -2

比較対象 EP1K100QC208-2N →

EP1K100QI208-3

Altera

Speed Grade: -3 (fastest)

Package: 208-pin PQFP (QFP, gull-wing)

✅ ドロップイン

Altera

📦 208-PQFP

ACEX-1K · Field Programmable Gate Array (FPGA) · 4992 · 624 · 49152 · 100K · 147 · 2.5 V

✓ 在庫あり

$19.5 / 個

データシートを見る →

EP1K100QC208-2N 最大定格＆電気的特性

Family	ACEX 1K
Device Type	FPGA (Field Programmable Gate Array)
Speed Grade	-2
Number of Logic Elements/Cells	4992
Number of LABs/CLBs	624
Total RAM Bits	49152
Maximum System Gates	257000
Number of User I/O	147
Core Supply Voltage	2.5 V
Technology	CMOS 0.22 um
Reported Clock Frequency	250 MHz
パッケージ	208-PQFP / 208-BFQFP
Package Code	FQFP
実装タイプ	Surface Mount
Terminal Form	Gull Wing
動作温度範囲	0C to 70C
ライフサイクル状態	Obsolete (EOL)

EP1K100QC208-2N fqfp ピン配置ガイド

EP1K100QC208-2N (fqfp パッケージ) のピン配置。このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

詳細なピン配置データはありません: EP1K100QC208-2N.

詳細はデータシートをご参照ください。

主な用途

EP1K100QC208-2N の用途: 6 件s: Communications Protocol Bridge, Industrial I/O and Machine Control, Video and Image Preprocessing, Test and Measurement Data Acquisition, Legacy System Lifecycle Replacement, SOPC / Soft Processor Subsystem.

🌐

Communications Protocol Bridge

The EP1K100QC208-2N is well suited for protocol bridging because its 147 user I/O can connect parallel legacy buses, UARTs, SPI and simple memory interfaces on the same device. The 4,992 logic elements implement FIFO controllers, packet parsers, CRC generators and bridge state machines without an external processor. Its 49,152 RAM bits can buffer packets or store small descriptor tables, reducing external SRAM count. At the -2 speed grade, typical byte-lane or serial bridge designs close timing comfortably below 100 MHz, simplifying PCB layout. Placed between a 3.3V I/O domain and 2.5V core, the device needs a 3.3V VCCIO rail and a 2.5V VCCINT rail. An EPC2 configuration device can make the bridge self-starting on power-up, an important reliability feature in telecom line cards.

おすすめ

EPC2 (Altera configuration device for storing ACEX 1K bitstream) EPC1 (Lower-cost configuration device for smaller bitstreams) EP1K100QC208-1N · Altera

🏭

Industrial I/O and Machine Control

In industrial control cards, the EP1K100QC208-2N can implement sensor input debounce, quadrature decoder logic, PLC-style output latching and fail-safe interlock logic. The 147 I/O pins allow direct connection to optocoupler inputs and transistor output stages, reducing glue components between the sensor interface and an external host processor. Commercial 0C to 70C operation suits indoor equipment racks and enclosed PLC cabinets with moderate airflow. Because the core is 2.5V and CMOS, idle power is modest compared with older 5V programmable logic. The 4,992 LEs provide ample resources for state-machine control, and 49,152 RAM bits can hold recipe tables or alarm logs. Use an EPC2 configuration device so the machine controller boots into a safe, defined state before the host CPU starts.

おすすめ

EPC2 (Reliable external boot memory for deterministic startup) EP1K100QC208-1N · Altera

📺

Video and Image Preprocessing

The EP1K100QC208-2N is appropriate for low-cost video preprocessing because it can perform pixel pipeline operations in parallel. Its 49,152 RAM bits can implement small line buffers for 3x3 convolution windows, and the 4,992 logic elements can handle thresholding, color-space conversion simple edge detection or pattern-of-interest windowing. A 2.5V core minimizes high-frequency switching noise on the pixel clock rail, important for maintaining image quality. The 208-pin PQFP provides enough I/O for a parallel camera bus plus output FIFO. At -2 speed, pixel clocks up to roughly 50-80 MHz are practical for moderate-resolution cameras. External video DACs or memory controllers still require glue logic, but the FPGA reduces the overall component count in legacy CCTV and industrial inspection modules.

おすすめ

EPC2 (Configuration device for autonomous video pipeline startup) EP1K100QC208-1GZ · Intel

🔧

Test and Measurement Data Acquisition

For benchtop instruments and custom DAQ boards, the EP1K100QC208-2N provides flexible glue logic between ADCs, DACs, counters and an embedded processor. The 147 user I/O can implement parallel AD7874-style converter buses, trigger routing and time-stamp counters. Its 4,992 logic elements are enough for a small FIFO controller and custom measurement state machine. The 49,152 RAM bits can store acquisition windows or act as a circular buffer for sporadic trigger events. The commercial temperature range fits indoor test equipment that is temperature-stabilized. Power dissipation is low enough for a 2.5V rail generated from a small LDO; however, designers must retain the external configuration source. For migrating an existing ACEX product, the -2N provides balanced speed and lead-free availability.

おすすめ

EPC1 (Configuration storage for benchtop instrument bitstream) EP1K100QC208-1N · Altera

🛠

Legacy System Lifecycle Replacement

The EP1K100QC208-2N is often used to replace the same MPN in equipment already deployed, because its 208-pin PQFP footprint and pinout are fixed by the original PCB. Field-service teams can substitute the -1N, -1 or -3N speed grades when the original -2N is unavailable, since all are pin-compatible and electrically compatible enough for many systems. The lead-free N suffix is beneficial for rework requiring modern solders. This application is about extending product life rather than new feature development. Prior to substitution, verify the configuration bitstream; if the original .sof/.pof was compiled for the same device family and pinout, it may work, but recompiling through Quartus II for the exact speed grade is safest.

おすすめ

EP1K100QC208-1N · Altera EP1K100QC208-2 · Altera EP1K100QC208-3N · Altera

🧩

SOPC / Soft Processor Subsystem

The ACEX 1K family was marketed as a low-cost system-on-a-programmable-chip platform, and the EP1K100QC208-2N can host small soft processors and memory-mapped peripherals. Its 4,992 logic elements are sufficient for a small Nios or custom 8/16-bit processor core, address decoding, UARTs and interrupt controllers. The 49,152 RAM bits are split among embedded array blocks to provide code and data storage without external SRAM. At -2 speed, a modest soft-core processor can execute control code while the FPGA simultaneously handles high-speed parallel I/O. Because ACEX 1K is SRAM-based, system designers must reset the processor into a valid state and load configuration from EPC1/EPC2. This architecture suits protocol converters needing both software flexibility and parallel hardware acceleration.

おすすめ

EPC2 (Configuration storage for soft-processor boot firmware) EP1K100QC208-1GZ · Intel

おすすめ製品の概要

EPC2 Altera configuration device for storing ACEX 1K bitstream 使用用途: Communications Protocol Bridge, Industrial I/O and Machine Control, Video and Image Preprocessing, SOPC / Soft Processor Subsystem EPC1 Lower-cost configuration device for smaller bitstreams 使用用途: Communications Protocol Bridge, Test and Measurement Data Acquisition EP1K100QC208-1N Altera 使用用途: Communications Protocol Bridge, Industrial I/O and Machine Control, Test and Measurement Data Acquisition, Legacy System Lifecycle Replacement EP1K100QC208-1GZ Intel 使用用途: Video and Image Preprocessing, SOPC / Soft Processor Subsystem EP1K100QC208-2 Altera 使用用途: Legacy System Lifecycle Replacement EP1K100QC208-3N Altera 使用用途: Legacy System Lifecycle Replacement

What is the EP1K100QC208-2N?

The EP1K100QC208-2N is an Altera ACEX 1K FPGA containing 4,992 logic elements, 624 LABs, 49,152 RAM bits and 147 user I/Os in a 208-pin PQFP package. It is designed for low-cost, high-volume system-on-a-programmable-chip applications. According to the ACEX 1K datasheet, the core supply rail is 2.5V and the commercial operating range is 0C to 70C. Intel/Altera now classifies the device as obsolete, but inventory remains at several distributors serving legacy maintenance and repair designs.

What are the key specifications of EP1K100QC208-2N that engineers should know?

Engineers evaluating the EP1K100QC208-2N should know that it contains 4,992 logic elements in 624 LABs, 49,152 RAM bits, 147 user I/O pins, and supports a 2.5V core supply. The package is a 208-pin PQFP/BFQFP with gull-wing leads. Verified listings report up to 257,000 system gates and a 250 MHz family clock listing. The operating temperature range is 0C to 70C, making it a commercial-temperature part. The -2 suffix indicates the speed grade; -1 is faster and -3 is slower in the same family.

Where can I buy EP1K100QC208-2N online?

You can buy the EP1K100QC208-2N from distributors such as DigiKey, Mouser, Octopart, Xecor and specialized obsolete-component brokers. DigiKey's product listing for this Altera FPGA shows an orderable status, and Octopart tracks inventory across 23 distributors. Since the part is obsolete, buyers should verify stock and date codes before releasing a BOM. XAIPART can source the EP1K100QC208-2N for small or large legacy-production quantities; request a quote to confirm availability and current pricing.

What is the price of EP1K100QC208-2N as of September 2026?

As of September 6, 2026, estimated single-unit pricing for the EP1K100QC208-2N is approximately $24.33, decreasing to about $16.42 at qty-1000 when available. These prices are estimates because the latest web snapshot did not include a confirmed distributor price table. Obsolete ACEX 1K parts often carry a premium on broker markets, so buyers should compare DigiKey, Mouser, Octopart and XAIPART quotes. Availability and pricing can change quickly for EOL components.

Is the EP1K100QC208-2N still in stock or available?

The EP1K100QC208-2N is still orderable in limited distributor stock, but its lifecycle status is obsolete. DigiKey shows an 'order today, ships today' status, and Mouser lists it with a datasheet and inventory page; however, Intel/Altera no longer manufactures the device. OEMs should treat inventory as depleting and consider lifetime buy provisions. Octopart is the recommended live cross-distributor tool to check current stock, because broker and authorized channels may change availability week to week.

EP1K100QC208-2N vs EP1K100QC208-1N: which is better?

The EP1K100QC208-1N is a faster -1 speed-grade version, while the EP1K100QC208-2N is the -2 version of the same EP1K100 die. Both share the 208-pin PQFP footprint, 4,992 logic elements, 49,152 RAM bits and 147 I/O pins, so they are pin-compatible. Choose the -1N when timing margins are tight and the design needs the extra performance. Choose the -2N when the design closes timing at the slower grade, because -2 stock is generally the more common obsolete-part inventory and may offer better cost and availability.

What is the difference between EP1K100QC208-2N and EP1K100QC208-2?

The EP1K100QC208-2N and EP1K100QC208-2 are electrically the same -2 speed-grade EP1K100 FPGA in the same 208-pin PQFP package. The main difference is the suffix: 'N' in Altera naming typically designates a lead-free finish, while the non-N version may use a non-lead-free finish. If your assembly process requires RoHS-compatible lead-free reflow, prefer the -2N variant. For leaded-solder or exempt processes, the -2 variant can be used as a drop-in after solderability qualification.

When should I choose EP1K100QC208-2N over EP1K100QC208-3N?

Choose the EP1K100QC208-2N over the EP1K100QC208-3N when you need more timing margin than the slower -3 speed grade provides. Both devices share identical logic resources and the same 208-pin PQFP package, so a board designed for one can accept the other. The -2 grade is one speed bin faster than -3, making it safer for datapaths with tighter propagation-delay requirements. If the design has generous timing margins and -3N stock is cheaper or more available, retiming with -3N may be acceptable, but the -2N is the safer default for legacy replacement.

Should I use EP1K100QC208-2N in a new design?

No, you should not use the EP1K100QC208-2N in a new high-volume design because it is obsolete and Intel/Altera has classified ACEX 1K as end-of-life. It remains appropriate for repairing or extending an existing ACEX 1K product, or for designs where the PCB and config bitstream are already frozen. New designs should target a currently supported FPGA family, such as Intel Cyclone or Agilex, to avoid future supply risk. If you must continue using this part, perform a lifetime buy and store devices in dry-pack conditions.

What is the best drop-in replacement for EP1K100QC208-2N?

The best drop-in replacements for the EP1K100QC208-2N are other EP1K100QC208 variants in the same 208-pin PQFP package: EP1K100QC208-2, EP1K100QC208-1N, EP1K100QC208-1 and EP1K100QC208-1GZ are pin-compatible speed or finish variants; EP1K100QC208-3N is a slower -3 grade but still same footprint. Because FPGA pinouts are proprietary, no known cross-brand Xilinx or Lattice part can be dropped onto the ACEX QC208 footprint without a PCB redesign. For legacy systems, first test the replacement with the original configuration bitstream and timing report.

Can EP1K100QC208-1N replace EP1K100QC208-2N?

Yes, the EP1K100QC208-1N can replace the EP1K100QC208-2N as a drop-in because it uses the same 208-pin PQFP package, the same 4,992 logic elements, the same 49,152 RAM bits and the same 147 I/O pins. The -1N is a faster speed grade, so a -2 configuration should fit timing if the design already meets requirements. You should recompile or at least re-verify timing in Quartus II with the -1N device selected, and confirm that the bitstream is generated for the same package and I/O standards. No PCB footprint change is required.

Where can I download the EP1K100QC208-2N datasheet PDF?

The EP1K100QC208-2N datasheet can be downloaded from datasheet aggregation pages returned in verified web results, including datasheets.com, DigChip, GlobalSpec and FindIC. For the family-level ACEX 1K documentation, search Intel's FPGA literature site for the ACEX 1K datasheet. A direct Intel PDF was not present in the fetched web snapshot, so use the datasheets.com URL as the most direct acess point, then cross-check the family pin list and electrical tables with the ACEX 1K device handbook.

What package does the EP1K100QC208-2N use and where is the pinout?

The EP1K100QC208-2N is packaged in a 208-pin plastic quad flat pack, labeled by distributors as 208-PQFP or 208-BFQFP, with gull-wing terminals and a square body. It exposes 147 user I/O pins plus dedicated power, ground, configuration and JTAG pins. Pin 1 location and full pin numbering are specified in the ACEX 1K datasheet pin file; because the 208-pin assignment table is too large for the verified web snippets, download the family datasheet or use Altera pin-out files to confirm exact pin names before PCB layout.

Is there a Xilinx or Lattice equivalent for EP1K100QC208-2N?

No Xilinx or Lattice FPGA is a pin-compatible drop-in equivalent for the EP1K100QC208-2N. FPGA I/O assignments, power pin locations and configuration schemes are proprietary, so cross-brand replacement requires a new PCB layout and bitstream. A different manufacturer part can only be a functional alternative at the board level, not a drop-in. For a redesign, a Xilinx Spartan or Lattice ECP device could implement similar logic capacity, but the design would need new pin assignments, power rails, configuration memory and timing constraints. Such migration is justified when moving away from the obsolete ACEX 1K family.

エンジニアリング参考データ: EP1K100QC208-2N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP1K100QC208-2N only when maintaining a legacy ACEX 1K board whose 208-pin PQFP footprint and -2 speed grade already pass timing. For high-volume production, verify stock first because the part is EOL. If timing margin is tight, use EP1K100QC208-1N or EP1K100QC208-1 (same package, faster -1 grade). If timing margins are wide and cost or availability favors a slower part, EP1K100QC208-3N can be considered after retiming. Avoid EP1K100QC208-2 if your assembly process is RoHS-controlled and you cannot verify lead-free finish; prefer the -2N. For new designs, do not choose ACEX 1K at all; move to a current FPGA family such as Intel Cyclone or Agilex. No cross-brand drop-in FPGA exists, so outside ACEX 1K a full PCB redesign is required.

代替品との比較

パラメータ	この製品	EP1K100QC208-2	EP1K100QC208-1N	EP1K100QC208-1	EP1K100QC208-1GZ	EP1K100QC208-3N
Brand / Manufacturer	Altera (Intel)	Altera	Altera	Altera	Altera	Altera
Package	208-PQFP / 208-BFQFP	208-PQFP / 208-BFQFP	208-PQFP / 208-BFQFP	208-PQFP / 208-BFQFP	208-PQFP / 208-BFQFP	208-PQFP / 208-BFQFP
Speed Grade	-2	-2	-1	-1	-1	-3
Logic Elements / Cells	4992	4992	4992	4992	4992	4992
LABs / CLBs	624	624	624	624	624	624
Total RAM Bits	49152	49152	49152	49152	49152	49152
Number of User I/O	147	147	147	147	147	147
Core Supply Voltage	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Operating Temperature Range	0C to 70C	0C to 70C	0C to 70C	0C to 70C	0C to 70C	0C to 70C

主な差別化要因

The -2N offers a lead-free-compatible N suffix at the most common speed grade for legacy ACEX 1K stock （vs EP1K100QC208-2)
Provides an intermediate timing option that balances cost and speed in the ACEX 1K QC208 family （vs EP1K100QC208-3N)
Same die, same pinout, same package across the EP1K100QC208 speed variants, allowing field substitution （vs EP1K100QC208-1N)

設計ノート

The EP1K100QC208-2N core rail is 2.5V, while I/O banks typically run at the interface voltage, commonly 3.3V. Decouple each VCC and VCCIO pin group with a 0.1uF ceramic capacitor and provide 1uF to 10uF bulk capacitance near the package. Estimated: if the configured design uses roughly 60% of logic and internal toggling, core current may be on the order of 0.2A to 0.5A, so the 2.5V supply should be rated for at least 1A. Keep the 2.5V plane separate from the 3.3V I/O plane to prevent noise coupling into the FPGA core.

The ACEX 1K EP1K100 is SRAM-based and has no nonvolatile configuration memory. If you omit an EPC1/EPC2 configuration device or fail to drive configuration from a host, the FPGA will not implement the intended logic after power-up. During configuration, I/O pins are typically tri-stated, so outputs connected to powered loads must have external pull-ups or enable logic to avoid indeterminate states. After configuration, verify CONF_DONE goes high and INIT_DONE behavior matches the ACEX 1K datasheet before releasing the board to production.

The 208-pin PQFP has a fine lead pitch, typically 0.5 mm on a 28 mm square body; follow manufacturer footprint recommendations for pad size and solder paste. Use 4-6 mil traces for fanout between leads, and place via-in-pad only if the assembly house supports it. A solid ground plane under the package is critical, and a thermal relief pattern should connect the large pad areas while maintaining electrical integrity. Add test points for the 2.5V and 3.3V rails and for key configuration signals DCLK, DATA0, nCONFIG and CONF_DONE.

コンプライアンス情報

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Unknown

ハロゲンフリー

Unknown

紛争鉱物

Unknown

The N suffix in Altera naming often indicates a lead-free finish, but the verified web data did not provide an explicit RoHS certificate or compliance statement. End-of-life status is confirmed by distributor/GlobalSpec records.

データ検証日: 2026-09-06 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Manufacturer Datasheet, Distributor, Distributor, Distributor, Distributor, Manufacturer Datasheet, Octopart, Distributor, Distributor