EP20K400CF672C7 - APEX 20KC FPGA, 400K Gates, 672-BGA | Intel
部品番号: EP20K400CF672C7 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268.5 | $2,685.00 |
| 100 | $242 | $24,200.00 |
| 500 | $218.75 | $109,375.00 |
| 1,000 | $195 | $195,000.00 |
EP20K400CF672C7 概要
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory, programmable interconnect, and I/O cells, all controlled by a user-defined bitstream. In the system hierarchy, FPGAs sit between general-purpose processors and fixed-function ASICs - offering hardware-level parallelism and design flexibility while consuming more power than purpose-built ASICs. The APEX 20KC family further extends this concept with MultiCore™ architecture combining look-up-table (LUT) logic with embedded system blocks (ESBs) that double as RAM, ROM, or content-addressable memory.
Key features of the EP20K400CF672C7 include 488 maximum user I/Os, 212,992 RAM bits, 2.5 ns pin-to-pin propagation delay, and up to 375.94 MHz internal operation. The 672-ball FineLine BGA package supports high-speed signal integrity for parallel buses, LVDS, and DDR memory interfaces, while the speed grade "-7" represents the mid-tier (commercial 0 °C to 85 °C) timing bin. The device also integrates 4 phase-locked loops (PLLs) for clock management and supports multi-voltage I/O standards including LVTTL, LVCMOS, PCI, SSTL, and LVDS.
The APEX 20KC architecture combines a fine-grained LUT fabric with coarse-grained embedded system blocks (ESBs), giving designers a flexible mix of distributed and block memory alongside high-speed parallel logic. This MultiCore™ approach was Altera's first SOPC-integrated PLD family, enabling single-chip processor-plus-logic subsystems using soft cores such as Nios®, Excalibur, or third-party IP. The 0.15 µm process technology balances density and power efficiency for the era's leading-edge telecom, networking, and DSP applications.
Typical applications include high-speed telecommunications backplanes, ASIC prototyping, DSP co-processors, parallel data acquisition, and bus-interface bridging. Designers choose the EP20K400CF672C7 when designs need hundreds of thousands of gates with abundant block RAM, sub-3 ns tPD, and abundant user I/O for parallel interfaces.
When designing with this FPGA, budget power carefully: a fully utilized EP20K400CF672C7 can exceed 3 W dynamic dissipation, requiring controlled-impedance PCB routing, solid ground/power planes, and thermal management of the BGA substrate. Verify Quartus® II (or Max+Plus® II legacy) bitstream compatibility before board bring-up.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the APEX 20KC datasheet - giving engineers a single reference for sourcing, replacement selection, and design-in guidance for legacy Altera APEX platforms.
ドロップイン代替品: EP20K400CF672C7 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K400CF672C7 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Process Technology, Speed Grade, Logic Elements.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K400CF672C-7ES
✅ ドロップイン✓ 在庫あり
$132 / 個
データシートを見る →EP20K400CF672C-8
✅ ドロップイン✓ 在庫あり
$95 / 個
データシートを見る →EP20K400CB652C9
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$89.2 / 個
データシートを見る →EP20K400EFC672-1XN
✅ ドロップイン✓ 在庫あり
$215 / 個
データシートを見る →EP20K400CB652C9N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$195 / 個
データシートを見る →EP20K400CF672C7 最大定格＆電気的特性
| Series | APEX-20KC |
| Family | APEX 20KC (MultiCore™) |
| Logic Elements / Cells | 16,640 |
| System Gates | 400,000 |
| Embedded Memory (RAM bits) | 212,992 |
| Maximum User I/O | 488 |
| Number of I/O Banks | 8 |
| パッケージ | 672-BBGA (FC-FBGA, FineLine BGA) |
| ピン数 | 672 |
| Core Voltage | 1.8 V |
| 電源電圧 | 2.5 V (I/O reference) |
| Process Technology | 0.15 µm CMOS |
| Propagation Delay (tPD) | 2.5 ns |
| Maximum Internal Frequency | 375.94 MHz |
| 動作温度 | 0 °C to +85 °C (Commercial, C-grade) |
| PLL Count | 4 |
| Speed Grade | -7 |
| 実装タイプ | Surface Mount (BGA) |
| RoHS ステータス | Non-compliant (legacy product) |
| Lead-Free | Contains lead (legacy BGA finish) |
EP20K400CF672C7 ピン構成
| ピン A1 | I/O Bank 1 — User I/O pin, Bank 1 (LVTTL/LVCMOS/LVDS) |
| ピン B2 | I/O Bank 1 — User I/O pin, Bank 1 |
| ピン C3 | GND — Ground |
| ピン D4 | VCCIO1 — I/O Bank 1 reference voltage (2.5 V or 3.3 V) |
| ピン E5 | I/O Bank 2 — User I/O pin, Bank 2 |
| ピン F6 | VCCINT — Core supply voltage (1.8 V) |
| ピン G7 | I/O Bank 3 — User I/O pin, Bank 3 |
| ピン H8 | PLL1_CLKp — PLL1 positive clock input |
| ピン J9 | PLL1_CLKn — PLL1 negative clock input |
| ピン K10 | I/O Bank 4 — User I/O pin, Bank 4 |
| ピン L11 | TCK — JTAG test clock input |
| ピン M12 | TMS — JTAG test mode select |
| ピン N13 | TDO — JTAG test data output |
| ピン P14 | TDI — JTAG test data input |
| ピン R15 | nCONFIG — Configuration control (active low) |
| ピン T16 | nSTATUS — Configuration status (active low) |
| ピン U17 | CONF_DONE — Configuration done indicator |
| ピン V18 | I/O Bank 5 — User I/O pin, Bank 5 |
| ピン W19 | I/O Bank 6 — User I/O pin, Bank 6 |
| ピン Y20 | VCCIO8 — I/O Bank 8 reference voltage |
主な用途
EP20K400CF672C7 の用途: 6 件s: Telecommunications Backplane, ASIC Prototyping, Digital Signal Processing (DSP), Parallel Data Acquisition, Bus Interface Bridging, Industrial Control Systems.
Telecommunications Backplane
The EP20K400CF672C7 fits telecom backplane designs thanks to its 488 user I/Os across 8 I/O banks, abundant LVDS-compatible transceivers, and 212,992 bits of embedded memory for buffer descriptors and lookup tables. The device's 2.5 ns propagation delay and 375.94 MHz internal frequency support STS-1/STM-1 line-card rates, while the 672-FBGA package routes 16-bit parallel buses and clock-distribution networks cleanly. Designers implement UTOPIA, POS-PHY, or SPI-4.2 interfaces using the abundant I/O and the four on-chip PLLs for jitter-cleaning. Versus a generic ASIC, the APEX 20KC's MultiCore™ architecture allows late-stage protocol changes without re-spinning silicon - critical for evolving 3G/UMTS backhaul standards.
おすすめ
ASIC Prototyping
Engineers use the EP20K400CF672C7 as a prototyping vehicle for 400K-gate ASICs because its 16,640 logic elements and 212,992 RAM bits match the density of mid-complexity application-specific designs. The MultiCore™ architecture integrates LUT logic with embedded system blocks (ESBs), allowing ASIC subsystems - including FIFOs, CAMs, and dual-port RAMs - to map directly onto APEX 20KC primitives. The 672-FBGA package offers enough I/O to bring out an entire ASIC's peripheral set for real-world stimulus testing. Quartus II synthesis flows can partition the design for fast iteration, while Altera's ByteBlaster and MasterBlaster configuration cables support rapid bitstream reload during validation.
おすすめ
Digital Signal Processing (DSP)
The EP20K400CF672C7 supports DSP co-processor designs where its 488 user I/Os and 212,992 embedded RAM bits provide ample bandwidth for parallel FIR filters, FFT butterflies, and video-processing pipelines. The four PLLs deliver multiple synchronized clock domains needed for ADC/DAC interface timing, while the 2.5 ns tPD accommodates systolic-array dataflow at sample rates up to 100 MHz. Engineers implement multiply-accumulate (MAC) units by mapping soft multipliers into the LUT fabric and storing coefficients in distributed RAM - a viable approach for moderate-throughput DSP such as audio sample-rate conversion or baseband modem blocks. Pairing the APEX 20KC with a dedicated DSP processor (e.g., ADSP-21160) yields a heterogeneous compute platform.
おすすめ
Parallel Data Acquisition
High-channel-count data acquisition systems rely on the EP20K400CF672C7 to aggregate multiple parallel ADC channels into a single FPGA pre-processing fabric. Its 488 user I/Os accept 8-/16-bit parallel LVCMOS or LVDS ADC outputs, while the 212,992 bits of embedded memory buffer block transfers before forwarding to a host CPU or DMA engine. The 375.94 MHz internal operation supports real-time decimation, FIR filtering, and event detection at sample rates exceeding 100 MHz. Designers exploit the four PLLs to align multiple ADC clock domains and reduce aperture-timing skew. The 672-FBGA package is well suited to controlled-impedance multi-layer PCBs used in instrumentation-grade front ends.
おすすめ
Bus Interface Bridging
The EP20K400CF672C7 is a natural fit for legacy-to-modern bus bridging designs - PCI to PCI Express, VME to Serial RapidIO, or parallel ATA to SATA translation. The 488 user I/Os accommodate both legacy wide buses (32-/64-bit PCI, 16-bit VME) and modern serialized links (LVDS pairs) simultaneously, while the embedded RAM blocks store translation tables and FIFOs for rate matching. The 2.5 ns tPD allows single-cycle protocol-state-machine transitions, and the four PLLs generate the multiple reference clocks required by asynchronous bridge topologies. The 672-FBGA package routes both directions cleanly with controlled impedance, simplifying signal-integrity closure for mixed-voltage domains.
おすすめ
Industrial Control Systems
Industrial control platforms benefit from the EP20K400CF672C7's high logic density for multi-axis motion control, machine vision preprocessing, and real-time EtherCAT/Profibus interface aggregation. The 488 user I/Os handle quadrature encoder inputs, PWM outputs, and parallel sensor buses simultaneously, while the embedded 212,992-bit RAM block provides zero-speed/position lookup tables for servo loops. The four PLLs synchronize motor PWM carriers and ADC sample clocks, reducing jitter on critical feedback paths. Although the part's commercial 0-85 °C rating limits deployment to cabinet-grade applications, the industrial-temperature variant EP20K400EFC672-1XN extends coverage to harsh factory environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K400CF672C7 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K400CF672C-7ES | EP20K400CF672C-8 | EP20K400EFC672-1XN |
|---|---|---|---|---|
| Package | 672-FBGA | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 |
| Speed Grade | -7 (375.94 MHz) | -7 | -8 (slower) | -1X (faster) |
| Operating Temperature | 0 to 85 °C (Commercial) | Extended (ES suffix) | 0 to 85 °C | Industrial (-40 to 100 °C) |
| Embedded Memory | 212,992 bits | 212,992 bits | 212,992 bits | 212,992 bits |
| Maximum User I/O | 488 | 488 | 488 | 488 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (NRND) |
主な差別化要因
- Mid-tier speed grade balances cost and performance for most designs （vs EP20K400CF672C-8)
- Standard commercial temperature rating is sufficient for most indoor designs （vs EP20K400EFC672-1XN)
- APEX 20KC MultiCore™ architecture supports ESB memory blocks for soft-CPU subsystems （vs EP20K400CB652 (652-BGA package))
設計ノート
Estimated: at full utilization the EP20K400CF672C7 dissipates 2-4 W dynamic power, but the FineLine BGA package can exceed 35 °C/W θJA without a heat-spreader. Use a 6-layer PCB with a dedicated inner ground plane beneath the BGA to spread heat; for industrial deployments consider a thermally-enhanced socket or metal heat-spreader attached to the package lid.
The 672-FBGA ball pitch is 1.0 mm, requiring 0.5 mm drilled microvias on the BGA-side PCB layers. Fan-out routing must escape between balls with at most two tracks per channel; use buried vias for signal layers deeper in the stack. Maintain 50 Ω single-ended / 100 Ω differential impedance for LVDS pairs and provide reference planes on adjacent layers for all high-speed signals.
Do not confuse the EP20K400CF672C7 with the EP20K400CB652 (652-ball BGA package) - the ball-maps are not pin-compatible despite similar logic density. Configuration bitstreams are NOT portable across speed grades (-7 vs -8 vs -1X); each speed grade requires recompilation in Quartus II. The part is not RoHS compliant - EU production requires the lead exemption documentation or a Cyclone IV GX migration.
コンプライアンス情報
RoHS non-compliant - legacy 0.15 µm Altera FBGA uses leaded ball finish. AEC-Q100 not applicable (FPGA, not automotive-qualified). REACH, halogen-free, and conflict-mineral data not published for this obsolete part.
