EP20K400CF672C9N - APEX 20KC 400K Gates FPGA | Intel (Altera)
部品番号: EP20K400CF672C9N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $255 | $2,550.00 |
| 100 | $220 | $22,000.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $175 | $175,000.00 |
EP20K400CF672C9N 概要
What is an FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated hardware resources such as block RAM, DSP slices, and high-speed transceivers. FPGAs sit at the top of the programmable logic hierarchy: ASIC -> programmable SoC -> FPGA -> CPLD -> PLD. APEX 20KC devices in particular introduced copper interconnect to Altera's high-density PLD roadmap, providing 25-35% higher performance than the APEX 20KE family while remaining pin-compatible.
Key features include 16,640 logic elements, 212,992 bits of embedded memory distributed across embedded system blocks, 502 user I/O pins, and propagation delay of approximately 2.5 ns per logic element. The MultiCore architecture integrates LUT-based logic and dual-port RAM blocks within the same fabric, allowing designers to implement complex state machines, FIFOs, and datapath functions without external memory.
The APEX 20KC family is built on a 0.18-micron six-layer copper-metal CMOS process. The 1.8V core supply reduces power consumption compared with the 2.5V APEX 20KE family while supporting LVCMOS, LVTTL, SSTL, and HSTL I/O standards through configurable I/O banks. The Fine-pitch Chip-Scale BGA package maximizes logic-to-pin density for high-I/O designs.
Typical applications include telecommunications infrastructure, high-speed data buffering, glue logic replacement, protocol bridging, and digital signal processing front-ends. The combination of high logic density and substantial embedded memory makes the EP20K400CF672C9N well suited to data-path aggregation and packet-processing pipelines.
When designing with this device, plan power sequencing carefully. The 1.8V core requires a low-noise LDO such as a TPS7A4701; the I/O banks need separate 3.3V or 2.5V rails depending on the chosen I/O standard. Decoupling capacitors must be placed as close as possible to each power pin on the BGA.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical FPGA design notes not found in the standalone manufacturer datasheet.
ドロップイン代替品: EP20K400CF672C9N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K400CF672C9N （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Process Technology, Propagation Delay, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K400CF672C9
✅ ドロップイン✓ 在庫あり
$390.4 / 個
データシートを見る →EP20K400CF672C8N
✅ ドロップイン✓ 在庫あり
$68.4 / 個
データシートを見る →EP20K400CF672C7N
✅ ドロップイン✓ 在庫あり
$160 / 個
データシートを見る →EP20K400CF672C9ES
✅ ドロップイン✓ 在庫あり
$168 / 個
データシートを見る →EP20K400CF672C8
✅ ドロップイン✓ 在庫あり
$108 / 個
データシートを見る →EP20K400CF672C8ES
✅ ドロップイン✓ 在庫あり
$158.4 / 個
データシートを見る →EP20K400CF672C9N 最大定格＆電気的特性
| Family | APEX 20KC |
| Series | EP20K400 |
| Logic Elements | 16,640 |
| System Gates | 400,000 |
| Maximum Operating Frequency | 250 MHz |
| Propagation Delay | 2.5 ns |
| User I/O Pins | 502 |
| Total I/O Lines | 480 |
| Dedicated Inputs | 4 |
| Embedded Memory | 212,992 bits |
| Core Voltage | 1.8 V |
| Process Technology | 0.18 µm all-layer copper CMOS |
| パッケージ | 672-ball FC-FBGA |
| 動作温度 | 0 °C to 85 °C (commercial) |
| RoHS ステータス | Compliant |
EP20K400CF672C9N 672-ball fc-fbga ピン配置ガイド
EP20K400CF672C9N (672-ball fc-fbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP20K400CF672C9N.
詳細は データシート をご参照ください。
主な用途
EP20K400CF672C9N の用途: 6 件s: Telecommunications Infrastructure, High-Speed Data Buffering and FIFO Aggregation, Glue Logic Replacement and Board Integration, Industrial Control and Factory Automation, Legacy Compute System / PCI Bridge Logic, Test and Measurement Equipment Front-End.
Telecommunications Infrastructure
The EP20K400CF672C9N's 16,640 logic elements and 502 user I/Os make it well suited to telecom backplane bridging, where wide parallel buses, ATM/SONET framers, and TDM switching fabrics need high gate counts and abundant I/O. Its 1.8V core and 250 MHz fabric deliver enough throughput for OC-48 framing glue logic, while the FC-FBGA 672-ball footprint supports the many LVDS pairs typically required for backplane serial links. Designers place the part on a multi-layer PCB with split power planes and per-bank VCCIO for 3.3V/2.5V/1.8V I/O standards.
おすすめ
High-Speed Data Buffering and FIFO Aggregation
With 212,992 bits of embedded memory distributed across ESBs (Embedded System Blocks), the EP20K400CF672C9N can implement large multi-channel FIFOs and packet buffers without external SRAM. The MultiCore architecture combines LUT logic with dual-port RAM in the same fabric, so designers can build 36-bit-wide FIFOs and store-and-forward datapaths in a single device. The 250 MHz fabric clock and 2.5 ns propagation delay support line-rate aggregation of multiple parallel data streams in networking line cards.
おすすめ
Glue Logic Replacement and Board Integration
The EP20K400CF672C9N replaces multiple discrete PAL/GAL and 74-series glue-logic devices on legacy backplanes, integrating address decoding, bus arbitration, wait-state generation, and interrupt steering in a single programmable IC. Its 502 user I/Os accommodate many parallel interfaces simultaneously, and its 1.8V core reduces board power. The 672-ball FC-FBGA package suits high-density backplanes where board real-estate is constrained.
おすすめ
Industrial Control and Factory Automation
Industrial controllers benefit from the EP20K400CF672C9N's large gate count and many I/Os to integrate multi-axis motion control, encoder decoding, and high-speed machine-vision preprocessing. The commercial 0-85 °C operating range suits factory-floor enclosures with controlled climate, and the abundant I/O allows direct connection to quadrature encoders, stepper/direction drivers, and parallel ADC/DAC buses without external buffers.
おすすめ
Legacy Compute System / PCI Bridge Logic
Before modern soft-IP cores, the APEX 20KC family was commonly deployed as a PCI-to-local-bus bridge and DMA controller in single-board computers and embedded x86 designs. The EP20K400CF672C9N's 502 I/Os accommodate 32-bit PCI plus local bus plus auxiliary peripherals in one device. The 1.8V core, 250 MHz fabric, and 2.5 ns internal delay allow zero-wait-state bridges up to 66 MHz PCI.
おすすめ
Test and Measurement Equipment Front-End
Test-equipment manufacturers used the EP20K400CF672C9N as a digital pattern generator, timing engine, or waveform pre-processor in bench-top instruments. Its 16,640 logic elements and high I/O count allow hundreds of digital channels with per-channel timing control, while embedded memory supports deep capture buffers. The 672-ball FC-FBGA package routes cleanly to fine-pitch test connectors and high-density mixed-signal daughtercards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K400CF672C9N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K400CF672C9 | EP20K400CF672C8N | EP20K400CF672C7N | EP20K400CF672C9ES | EP20K400CF672C8 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA (same) | 672-ball FC-FBGA (same) | 672-ball FC-FBGA (same) | 672-ball FC-FBGA (same) | 672-ball FC-FBGA (same) |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 |
| System Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 |
| User I/Os | 502 | 502 | 502 | 502 | 502 | 502 |
| Speed Grade | -9 (C9) | -9 | -8 (~10% slower) | -7 (~20% slower) | -9 ES | -8 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Highest speed grade in the EP20K400 family （vs EP20K400CF672C8N)
- Lead-free and Pb-free terminal finish (N suffix) （vs EP20K400CF672C9)
- Same-footprint compatibility with the APEX 20KE family （vs EP20K400EFC672-1N)
設計ノート
The APEX 20KC family requires a low-noise 1.8V core supply for VCCINT plus independently configurable VCCIO rails per I/O bank (commonly 3.3V, 2.5V, or 1.8V). Use a low-dropout regulator such as the TPS7A4701 for VCCINT and per-bank LDOs (e.g., TPS73633) for VCCIO. Bulk-decoupling with 100 µF tantalum plus 0.1 µF/10 nF ceramics per power pin is recommended. Estimated: at full toggle rate with 502 I/Os switching, the device can draw 1.5-2.5 A from VCCINT.
The 672-ball FC-FBGA package uses 1.0 mm ball pitch and requires microvia or via-in-pad technology for reliable breakout. Place at least one 0402 decoupling cap per power pin on the opposite PCB side directly under the BGA array. Use a 1 oz copper power plane for VCCINT and split VCCIO planes per bank to isolate noise. Maintain a continuous ground plane on layer 2 to provide low-impedance return paths for high-speed LVDS pairs.
Do not confuse the APEX 20KC (C-suffix, 1.8V core) with the APEX 20KE (E-suffix, 2.5V core). Although the 672-ball FC-FBGA pinout is shared between families, the core voltage and configuration bitstream are not interchangeable - applying 2.5V to a C-suffix part will damage it. Also confirm that the configuration device (typically an EPC2 or EPC16) matches the chosen speed grade, otherwise JTAG configuration may fail intermittently at temperature extremes.
コンプライアンス情報
The 'N' suffix in EP20K400CF672C9N indicates a Pb-free (lead-free) terminal finish compliant with RoHS. The part is now obsolete and not recommended for new designs; commercial 0-85 °C temperature grade only. AEC-Q100 is not applicable since this is an FPGA, not a discrete automotive IC.