EP20K600CB672C7 - APEX 20KC FPGA 600K Gates 672-BGA | Altera
部品番号: EP20K600CB672C7 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $232.5 | $2,325.00 |
| 100 | $215 | $21,500.00 |
| 500 | $198.75 | $99,375.00 |
| 1,000 | $182.5 | $182,500.00 |
EP20K600CB672C7 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (LABs), embedded memory, and programmable interconnect that the user can program to implement arbitrary digital logic. Within the broader hierarchy it sits as: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit. The APEX 20KC family extends this with MultiCore blocks that combine look-up tables, product-term logic and dual-port embedded SRAM on a single die, allowing a single chip to host microcontrollers, DSP datapaths, and wide memory arrays.
Key features of the EP20K600CB672C7 include 30,960 typical logic elements, approximately 311 kbits of embedded SRAM distributed across embedded array blocks (EABs), support for LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL and CTT I/O standards, four phase-locked loops (PLLs) for clock conditioning, and 4.5 ns dual-port RAM access. It is built on a 2.5 V core supply with MultiVolt I/O support from 1.8 V to 3.3 V.
The C7 speed grade designates a commercial temperature grade (0 °C to 85 °C) and a 7-class performance bin. The 0.15 µm copper process yields roughly 35% higher design performance than the original APEX 20KE devices, while the FineLine BGA offers high pin density suitable for telecom backplanes, ASIC prototyping, and high-speed datapath glue logic.
Typical applications for the EP20K600CB672C7 include high-speed telecommunications line cards, ATM/Sonet/SDH framers, DSLAM datapaths, PCI bus bridging, graphics/video processing, ASIC prototyping, and DSP co-processing. The 600K-gate capacity and dual-port embedded memory make it a strong fit for designs that previously required multiple FPGAs or a discrete ASIC.
When designing with this device, plan power sequencing for the 2.5 V VCCINT and the 1.8 V/2.5 V/3.3 V VCCIO rails, ensure decoupling follows the Quartus APR recommendations, and select the C7 grade only when timing closure is met; faster C8/C9 grades cost more. This page synthesizes distributor pricing, APEX 20KC drop-in alternatives, and practical Quartus design notes not found in the manufacturer datasheet.
ドロップイン代替品: EP20K600CB672C7 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K600CB672C7 （同一形状・フットプリント） — 相違点: Package, Process Technology, Speed Grade, Operating Temperature, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K600CB672C8
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$245 / 個
データシートを見る →EP20K600CB672C9
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K600CB672I7
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K600CB672I8
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K600CB672C7N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K600CB672C8N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$69 / 個
データシートを見る →EP20K600CB672C7 最大定格＆電気的特性
| Family | APEX 20KC |
| Device Type | FPGA / Programmable Logic Device (PLD) |
| Typical Gates | 600,000 |
| Maximum System Gates | 1,053,840 |
| Logic Elements | 30,960 (typical) |
| Embedded Memory | 311 kbits (EAB-based) |
| User I/Os | 488 |
| パッケージ | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) |
| Speed Grade | C7 (commercial, 0 °C to 85 °C) |
| Propagation Delay | 1.48 ns |
| Process Technology | 0.15 µm all-layer copper-metal CMOS |
| Core Voltage | 2.5 V |
| I/O Voltage Support | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) |
| Number of PLLs | 4 |
| Dual-Port RAM | Yes (4.5 ns access) |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT |
| 動作温度 | 0 °C to 85 °C (commercial) |
| Configuration Method | EPC configuration devices / JTAG / passive serial |
| RoHS ステータス | Compliant |
EP20K600CB672C7 ピン構成
| ピン A1 | I/O / GND — User I/O or power/ground ball (refer to APEX 20K family datasheet for exact assignment) |
| ピン B1 | I/O / GND — User I/O or power/ground ball |
| ピン C1 | I/O / GND — User I/O or power/ground ball |
| ピン D1 | I/O — User I/O ball |
| ピン E1 | VCCINT — Core supply 2.5 V |
| ピン F1 | VCCIO — I/O supply (1.8 V / 2.5 V / 3.3 V) |
| ピン G1 | GND — Ground |
| ピン H1 | I/O — User I/O ball |
| ピン J1 | I/O — User I/O ball |
| ピン K1 | I/O — User I/O ball |
| ピン L1 | I/O — User I/O ball |
| ピン M1 | I/O — User I/O ball |
| ピン N1 | VCCINT — Core supply 2.5 V |
| ピン P1 | VCCIO — I/O supply |
| ピン R1 | GND — Ground |
| ピン A26 | TCK — JTAG clock |
| ピン B26 | TMS — JTAG mode select |
| ピン C26 | TDI — JTAG data in |
| ピン D26 | TDO — JTAG data out |
| ピン E26 | nCE — Chip enable (active low) |
| ピン F26 | nCONFIG — Configuration control (active low) |
| ピン G26 | nSTATUS — Configuration status (active low) |
| ピン H26 | DCLK — Configuration clock |
| ピン J26 | DATA0 — Configuration data 0 |
主な用途
EP20K600CB672C7 の用途: 6 件s: Telecom Line Cards (ATM / Sonet / SDH Framers), ASIC Prototyping & Logic Emulation, DSP Co-Processing & Signal Datapath Glue, PCI Bus Bridging & Embedded Backplanes, Network Switching & Router Line-Card Forwarding, Industrial Control & Motor Drive Logic.
Telecom Line Cards (ATM / Sonet / SDH Framers)
The EP20K600CB672C7 fits telecom line-card designs because its 600K typical-gate capacity and 488 user I/Os let a single device terminate multiple UTOPIA / POS-PHY data streams while hosting framer and cross-connect logic. The four on-chip PLLs clean up recovered clocks before the MultiCore blocks feed the embedded dual-port RAM (311 kbits) for cell buffering. Industrial-grade alternatives like EP20K600CB672I7 are preferred for outdoor cabinets.
おすすめ
ASIC Prototyping & Logic Emulation
Design teams use the EP20K600CB672C7 as a prototyping vehicle for ASICs in the 500K-1M gate range, because its 30,960 logic elements and 4.5 ns dual-port SRAM emulate large datapath and control blocks in parallel. The 672-ball FineLine BGA delivers 488 I/Os which is enough to map wide internal ASIC buses to off-chip observation pins. Quartus II design flow supports seamless migration to Cyclone IV / Stratix IV for production volumes.
おすすめ
DSP Co-Processing & Signal Datapath Glue
DSP co-processors benefit from the EP20K600CB672C7's EAB-based 311 kbits of dual-port SRAM, which can implement shift registers, FFT twiddle tables, and FIR coefficient buffers next to the multiplier datapath. The MultiCore architecture pairs LUTs with product-term logic, ideal for saturated arithmetic and saturation logic in video / image pipelines. The four PLLs let the FPGA lock to external DSP clocks at 33/66/100 MHz.
おすすめ
PCI Bus Bridging & Embedded Backplanes
The 488 user I/Os and 33/66 MHz PCI support in the EP20K600CB672C7 are well suited to bridging PCI/PCI-X buses to local processor or backplane fabrics. Designers typically instantiate a PCI core, dual-port RAM for posted-write buffers, and DMA engines in one chip. The 2.5 V core with MultiVolt I/O from 1.8 V to 3.3 V allows direct interface to legacy 3.3 V ASICs without level shifters.
おすすめ
Network Switching & Router Line-Card Forwarding
Router and L2/L3 switch line cards use the EP20K600CB672C7 to implement CAM controllers, lookup-table engines, and queue managers fed by 10/100/Gigabit Ethernet MACs. The four PLLs let one chip handle multiple clock domains for ingress, fabric, and egress paths, while the 311 kbits of embedded RAM store statistics counters at line rate. The 672-ball BGA provides enough I/O to connect to UTOPIA, SPI-4.2, or SGMII interfaces.
おすすめ
Industrial Control & Motor Drive Logic
In factory-automation cabinets the EP20K600CB672C7 implements PLC scan engines, motion-control state machines, and encoder-capture logic. The industrial-grade EP20K600CB672I7 variant is preferred where ambient temperatures exceed 70 °C. The MultiVolt I/O allows direct connection to 24 V-tolerant opto-isolated inputs via external resistor dividers, while the embedded dual-port RAM stores trajectory tables.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K600CB672C7 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K600CB672C8 | EP20K600CB672C9 | EP20K600CB672I7 | EP20K600CB672I8 | EP20K600CB672C7N | EP20K600CB672C8N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Speed Grade | C7 (commercial) | C8 (commercial, faster) | C9 (commercial, fastest) | I7 (industrial) | I8 (industrial, faster) | C7 (commercial, lead-free) | C8 (commercial, lead-free) |
| Operating Temperature | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | -40 °C to 100 °C | -40 °C to 100 °C | 0 °C to 85 °C | 0 °C to 85 °C |
| Typical Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| Embedded SRAM | 311 kbits | 311 kbits | 311 kbits | 311 kbits | 311 kbits | 311 kbits | 311 kbits |
| User I/Os | 488 | 488 | 488 | 488 | 488 | 488 | 488 |
| Lead-Free / RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Yes (N suffix) | Yes (N suffix) |
主な差別化要因
- Wider commercial temperature + speed grade options （vs EP20K600CF672C7)
- Industrial temperature variants drop-in compatible （vs EP20K600CB672I7 / I8)
- Lead-free (N-suffix) variants for RoHS projects （vs EP20K600CB672C7N)
設計ノート
The EP20K600CB672C7 requires a clean 2.5 V VCCINT supply capable of delivering up to 1.5 A in worst-case utilization. Use a 4-layer PCB with dedicated power planes and place 0.1 µF + 10 µF decoupling within 5 mm of every VCCINT ball group. The VCCIO rail (1.8 V / 2.5 V / 3.3 V) must ramp within 100 ms of VCCINT to avoid I/O latch-up; the APEX 20K datasheet recommends a sequenced hot-swap controller for hot-plug line-card designs.
The 672-ball FineLine BGA package has a θJA around 11 °C/W with a 1 oz copper inner plane; at 600 K-gate utilization with 100 MHz toggling, estimated power dissipation is 4-6 W. Use a thermal pad connected to the inner ground plane, and consider a small heatsink if the enclosure ambient exceeds 60 °C. For industrial temperature-grade variants (EP20K600CB672I7/I8) the junction-to-ambient thermal budget tightens further.
Route the 672-ball FineLine BGA with 1.27 mm pitch using 0.20 mm trace/space design rules and microvia-in-pad for the inner rows. Match the JTAG chain length within ±50 ps to avoid configuration shift errors. All configuration balls (nCE, nCONFIG, nSTATUS, DCLK, DATA0) require 4.7 kΩ pull-ups; MSEL[0:2] pins select the configuration mode and must be tied to VCCIO or GND with no stubs.
Do not confuse the CB672 BGA code with the CF672 code - they share the same 672-ball package but differ in user-I/O pin mapping. Swapping EP20K600CB672C7 with EP20K600CF672C7 will require a BGA escape re-spin. Also confirm that your Quartus II version supports the APEX 20KC family; Quartus 13.1 and earlier are required, while Quartus 14+ has dropped legacy device support.
コンプライアンス情報
RoHS and lead-free status confirmed via Altera product family documentation. AEC-Q100 not applicable - this is a commercial FPGA. Conflict-mineral / halogen-free data not present in verified sources.
