Altera

EP20K600CF672C-9 - 600K Gates APEX 20KC FPGA 488 I/O BGA-672 | Altera

部品番号: EP20K600CF672C-9 ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1.8 V Vdss 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) Package -9 Speed

開始価格 $171 USD / 個

MOQ: 1 |

価格更新日: 2026-09-07

ボリューム価格

数量	単価	小計
1	$285	$285.00
10	$256.5	$2,565.00
100	$228	$22,800.00
500	$199.5	$99,750.00
1,000	$171	$171,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP20K600CF672C-9 概要

The Altera EP20K600CF672C-9 is a member of the APEX 20KC family of programmable logic devices, delivering up to 600,000 typical gates of logic integration in a 672-ball fine-pitch BGA (FBGA) package. It is fabricated on a 0.15 µm all-layer copper interconnect process and is targeted at high-performance, high-density data-path and control-path designs. The device is configured at system power-up via a serial data stream from an Altera EPC16, EPC8, EPC4, EPC2, or EPC1 configuration device and supports in-system programmability (ISP) plus one-time programmable (OTP) modes.

What is an FPGA? An FPGA (Field-Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer can wire up after manufacture to implement arbitrary digital logic. APEX 20KC sits in the combined CPLD/FPGA hybrid category historically called "complex PLD" — its LUT-based MegaLAB structure combines coarse-grained PLD-style logic blocks with fine-grained FPGA-style routing. In the broader taxonomy, APEX 20KC belongs to: FPGA > programmable logic > logic IC > integrated circuit > semiconductor.

Key features of the EP20K600CF672C-9 include 30,560 logic elements (LEs), 488 user I/O pins, 1.8 V VCCINT core supply, and MultiVolt I/O supporting 1.8 V, 2.5 V, 3.3 V, and 5.0 V VCCIO levels. The device integrates embedded system blocks (ESBs) for RAM and ROM, four phase-locked loops (PLLs) for clock synthesis, and a four-level hierarchical interconnect structure built on copper metal for high performance. Speed grade -9 places this part in Altera's mid-tier performance bin for the APEX 20KC family.

The APEX 20KC architecture combines LUT-based logic with a high-speed interconnect fabric and dedicated multiplier/ESB blocks, giving designers a single-chip solution for datapath, control logic, and memory functions. The -9 speed grade and the four embedded PLLs support designs with tight clock-to-output budgets and complex clock trees typical of communications and image-processing pipelines.

Typical applications include telecommunications line cards, image and video processing hardware, DSP co-processing engines, high-speed data-acquisition front ends, and ASIC prototyping. The MultiVolt I/O also makes the device useful as a glue-logic bridge between legacy 5 V peripherals and modern 1.8 V / 3.3 V ASICs/CPUs.

When designing with this device, ensure that VCCINT is ramped cleanly to 1.8 V before configuration begins and that the chosen EPC16/EPC8/EPC4 configuration device matches the desired ISP or OTP mode. Decoupling follows the standard APEX 20KC guideline: at least one bulk 33 µF plus one 0.1 µF ceramic per VCCIO bank and a similar network on VCCINT and VCCPD.

This page synthesizes distributor pricing, APEX 20KC family drop-in variants, and practical configuration/PCB guidance that is not available in any single manufacturer datasheet or distributor product page.

ドロップイン代替品: EP20K600CF672C-9 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP20K600CF672C-9 （同一形状・フットプリント） — 相違点: Process Technology, Speed Grade, Package, Operating Temperature, Device Type.

EP20K600CB672C7

Altera

Process Technology: 0.15 µm all-layer copper-metal CMOS

Speed Grade: C7 (commercial, 0 °C to 85 °C)

Package: 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)

比較対象 EP20K600CF672C-9 →

EP20K600CF672

Intel

Process Technology: 0.15 um all-layer copper-metal process for supplied family references

Operating Temperature: 0 C to 85 C for supplied EP20K600CF672C9N/C8N references

比較対象 EP20K600CF672C-9 →

EP20K600CF672-3

Intel

Process Technology: 0.18 µm CMOS

Speed Grade: -3

Package: 672-ball FineLine BGA

比較対象 EP20K600CF672C-9 →

EP20K600CF672C-7

Altera

Process Technology: 0.18 µm all-layer copper-metal (APEX 20KC)

Speed Grade: -7

Operating Temperature: 0 °C to 85 °C (Commercial)

比較対象 EP20K600CF672C-9 →

EP20K600CF672C-7ES

Altera

Process Technology: 0.15 micron all-layer copper CMOS

Speed Grade: -7

Package: 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch

比較対象 EP20K600CF672C-9 →

EP20K600CF672C-8

Altera

Process Technology: 0.15 micrometer all-layer copper-metal

Speed Grade: -8

Device Type: FPGA (Field Programmable Gate Array)

比較対象 EP20K600CF672C-9 →

EP20K600CF672C6

Altera

Process Technology: 0.18 µm CMOS, 6 metal layers

Speed Grade: -6 (C6)

Package: 672-ball FineLine BGA (CF672)

比較対象 EP20K600CF672C-9 →

✅ ドロップイン

Altera

📦 672-ball BGA

APEX 20KC · FPGA / Programmable Logic Device (PLD) · 600,000 · 1,053,840 · 30,960 (typical) · 311 kbits (EAB-based) · 488 · 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)

✓ 在庫あり

$182.5 / 個

データシートを見る →

EP20K600CF672C-9 最大定格＆電気的特性

Device Type	FPGA (APEX 20KC family, complex PLD)
Typical Gate Count	600,000 gates
User I/Os	488 pins
PLLs	4
パッケージ	672-ball FBGA (45 x 45 mm, 1.27 mm pitch)
ピン数	672
Core Supply Voltage (VCCINT)	1.8 V
I/O Supply Voltage (VCCIO)	1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Propagation Delay	1.48 ns
動作温度	0 °C to +85 °C (commercial)
Speed Grade	-9
Process Technology	0.15 µm all-layer copper interconnect
Configuration Interface	Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1)
実装タイプ	Surface Mount (BGA)
RoHS ステータス	unknown

EP20K600CF672C-9 ピン構成

ピン 1	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 2	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 3	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 4	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 5	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 6	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 7	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 8	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 9	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 10	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 11	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 12	I/O Bank 1 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 13	VCCIO1 — I/O bank 1 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 14	GND — Ground
ピン 15	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 16	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 17	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 18	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 19	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 20	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 21	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 22	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 23	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 24	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 25	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 26	I/O Bank 2 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 27	VCCIO2 — I/O bank 2 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 28	GND — Ground
ピン 29	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 30	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 31	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 32	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 33	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 34	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 35	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 36	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 37	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 38	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 39	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 40	I/O Bank 3 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 41	VCCIO3 — I/O bank 3 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 42	GND — Ground
ピン 43	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 44	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 45	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 46	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 47	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 48	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 49	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 50	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 51	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 52	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 53	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 54	I/O Bank 4 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 55	VCCIO4 — I/O bank 4 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 56	GND — Ground
ピン 57	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 58	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 59	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 60	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 61	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 62	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 63	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 64	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 65	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 66	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 67	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 68	I/O Bank 5 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 69	VCCIO5 — I/O bank 5 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 70	GND — Ground
ピン 71	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 72	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 73	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 74	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 75	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 76	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 77	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 78	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 79	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 80	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 81	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 82	I/O Bank 6 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 83	VCCIO6 — I/O bank 6 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 84	GND — Ground
ピン 85	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 86	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 87	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 88	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 89	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 90	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 91	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 92	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 93	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 94	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 95	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 96	I/O Bank 7 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 97	VCCIO7 — I/O bank 7 supply voltage (1.8V / 2.5V / 3.3V / 5.0V)
ピン 98	GND — Ground
ピン 99	I/O Bank 8 — User I/O pin (MultiVolt, per bank assignment in datasheet)
ピン 100	I/O Bank 8 — User I/O pin (MultiVolt, per bank assignment in datasheet)

主な用途

EP20K600CF672C-9 の用途: 6 件s: Telecommunications Line-Card Logic, Image and Video Processing Pipelines, DSP Co-Processing Engine, High-Speed Data-Acquisition Front End, ASIC Prototyping Platform, Legacy Industrial Control Backplane.

🌐

Telecommunications Line-Card Logic

The EP20K600CF672C-9 fits telecommunications line-card designs because it integrates up to 600,000 gates, 488 MultiVolt I/Os, and 4 PLLs on a single die. Its 1.8 V core and 1.8 V / 2.5 V / 3.3 V / 5.0 V MultiVolt I/O make it straightforward to bridge legacy 5 V framer/mapper ASICs to modern 1.8 V or 2.5 V backplane SERDES. According to the APEX 20KC datasheet, the embedded system blocks provide enough on-chip RAM for cell/frame buffering, while the four PLLs handle multiple backplane reference clocks. Placement near the line-side connector reduces trace length for high-speed LVDS or PECL clocks.

おすすめ

🎥

Image and Video Processing Pipelines

The EP20K600CF672C-9 suits image and video processing pipelines because its 30K logic-element array and embedded system blocks can implement parallel pixel-processing datapaths, line buffers, and 2D convolution engines. The 488 user I/Os comfortably accept parallel video buses (8/16/24-bit RGB or YUV), camera-link interfaces, and DDR memory interfaces. The four PLLs derive multiple pixel clocks from a single reference, while the 1.8 V VCCINT minimizes dynamic power in always-on video applications. PCB layout should isolate high-speed video I/O banks from noisier analog rails.

おすすめ

EP20K600CF672C-8 · Altera

🖥️

DSP Co-Processing Engine

The EP20K600CF672C-9 functions as a DSP co-processor when paired with a host CPU, offloading FIR filters, FFTs, and convolutional encoders onto its parallel logic fabric. With 600K gates and embedded system blocks, designers can implement multiply-accumulate (MAC) pipelines that outperform general-purpose DSP ICs at fixed-function tasks. The MultiVolt I/O lets it interface directly to 3.3 V DSPs or 5 V legacy codecs, and the four PLLs support the multiple clock domains typical of mixed-rate DSP pipelines. Engineers should budget logic utilization at 70-80% to leave headroom for timing closure in Quartus.

おすすめ

EP20K600CF672 · Intel

🏭

High-Speed Data-Acquisition Front End

The EP20K600CF672C-9 is well-matched to high-speed data-acquisition front ends because its 488 user I/Os can capture parallel LVDS or CMOS ADC outputs, and its embedded system blocks provide the FIFO and ping-pong buffer memory needed for sustained sample rates. The four PLLs generate the ADC sample clocks and the system-side processing clocks from a single reference. MultiVolt I/O supports direct connection to 5 V or 3.3 V ADCs without external level shifters. According to the APEX 20KC datasheet, the device can also drive DDR memory interfaces for deep capture buffers.

おすすめ

EP20K600CF672C-7 · Altera

🧩

ASIC Prototyping Platform

The EP20K600CF672C-9 is frequently used as an ASIC prototyping vehicle because its LUT-based logic can map arbitrary RTL at high gate capacity, and its 672-ball FBGA exposes enough I/Os to bring out wide internal buses for logic-analyzer debugging. Quartus II supports the APEX 20KC family with the same synthesis flow used for Cyclone-series FPGAs, easing migration. Compared to building a mask-set ASIC, an APEX 20KC prototype cuts NRE to zero and allows firmware-ASIC co-development before tape-out. For multi-FPGA partitioning, multiple EP20K600CF672C-9 devices can be tiled together with shared clock and JTAG chains.

おすすめ

EP20K600CF672C-8 · Altera

⚡

Legacy Industrial Control Backplane

The EP20K600CF672C-9 is a practical solution for sustaining legacy industrial control backplanes whose firmware is locked to the APEX 20KC architecture. Its MultiVolt I/O (1.8 V / 2.5 V / 3.3 V / 5.0 V) bridges between modern 1.8 V control ASICs and legacy 5 V PLC I/O modules, and the 488 user I/Os are sufficient for full backplane fan-out without external bus transceivers. According to the APEX 20KC datasheet, the commercial 0 °C to +85 °C temperature range suits most factory-floor enclosures. For new designs, a Cyclone IV / Cyclone V should be considered instead, but for sustaining installed equipment, the EP20K600CF672C-9 remains a viable drop-in.

おすすめ

EP20K600CF672 · Intel

おすすめ製品の概要

EP20K600CF672C-8 Altera 使用用途: Telecommunications Line-Card Logic, Image and Video Processing Pipelines, ASIC Prototyping Platform EP20K600CF672C-7 Altera 使用用途: Telecommunications Line-Card Logic, High-Speed Data-Acquisition Front End EP20K600CF672 Intel 使用用途: DSP Co-Processing Engine, Legacy Industrial Control Backplane

What is the EP20K600CF672C-9?

The EP20K600CF672C-9 is an Altera APEX 20KC family complex programmable logic device (CPLD/FPGA hybrid) delivering up to 600,000 typical gates in a 672-ball fine-pitch BGA. According to the APEX 20KC datasheet, it provides 488 user I/Os, 4 PLLs, and a 1.8 V core supply with MultiVolt I/O supporting 1.8 V / 2.5 V / 3.3 V / 5.0 V. It is configured at power-up via a serial stream from an EPC16, EPC8, EPC4, EPC2, or EPC1 configuration device.

What package does the EP20K600CF672C-9 use?

The EP20K600CF672C-9 ships in a 672-ball fine-pitch BGA (FBGA) measuring 45 × 45 mm with a 1.27 mm ball pitch. Per the Altera APEX 20KC datasheet, this is a surface-mount package with MultiVolt I/O banks supporting 1.8 V, 2.5 V, 3.3 V, and 5.0 V VCCIO. PCB designers must allocate via-in-pad or standard BGA breakout routing for the 672 balls and observe the 1.0 mm or larger via-to-via clearance Altera recommends for fine-pitch BGAs.

What is the operating voltage of the EP20K600CF672C-9?

The EP20K600CF672C-9 operates with VCCINT = 1.8 V for the core logic and VCCIO = 1.8 V / 2.5 V / 3.3 V / 5.0 V (selectable per I/O bank) for MultiVolt I/O compatibility. According to the APEX 20KC datasheet, VCCPD must also be supplied to power the configuration logic. Both VCCINT and VCCIO rails must be ramped cleanly before configuration begins, otherwise the device may enter an undefined state.

Is the EP20K600CF672C-9 still in production?

No, the EP20K600CF672C-9 is listed as obsolete and is no longer in active production. The APEX 20KC family has been superseded by Altera's later Cyclone, Arria, and Stratix FPGA families (now under Intel FPGA). According to the Altera product discontinuation notices, APEX 20KC parts are typically available only through distributor excess stock and the secondary market; pricing reflects this scarcity as of 2026-09-08.

What is the difference between EP20K600CF672C-9 and EP20K600CF672C-8?

The EP20K600CF672C-9 and EP20K600CF672C-8 share the identical 672-ball FBGA package, identical 600K-gate APEX 20KC die, and identical electrical specifications. The only difference is the speed grade suffix: -9 is the mid-tier speed grade and -8 is a slightly faster speed grade (lower propagation delay). Both are obsolete Altera parts and are drop-in compatible at the PCB footprint level, though Quartus timing constraints must be regenerated for the chosen speed grade.

Where to buy EP20K600CF672C-9 online?

The EP20K600CF672C-9 is no longer in active production, so it is typically sourced through distributors carrying excess stock such as DigiKey, Mouser, Heisener, Sierra IC, Vyrian, and Octopart-listed vendors. As of 2026-09-08, Heisener reports approximately in stock; pricing varies widely across distributors and is generally quoted on request for obsolete parts. Buyers should verify lot date codes and request RoHS/REACH documentation, since original APEX 20KC material may predate RoHS transitions.

What is the price of the EP20K600CF672C-9?

The EP20K600CF672C-9 prices as of 2026-09-08 reflect its obsolete status; distributor list prices are typically in the 170–285 USD range depending on quantity break and lot acceptance. Tier-1 distributors (DigiKey, Mouser) often quote on request for obsolete parts, while secondary-market vendors (Heisener, Sierra IC, Vyrian) provide public per-piece pricing. For budgeting purposes, plan approximately 199.50 USD per piece at the 500-piece break, plus any reel/lot premium for date-code compliance.

What is the lead time for the EP20K600CF672C-9?

Lead time for the EP20K600CF672C-9 as of 2026-09-08 is variable because the part is obsolete and no longer in active production. Distributors carrying stock typically ship within 5–15 business days after order acceptance, while quotes from secondary-market vendors may take 3–7 days to confirm availability. For production builds requiring date-code compliance, expect 4–8 weeks because vendors may need to source from multiple excess-channel lots.

Is the EP20K600CF672C-9 in stock anywhere?

Yes, the EP20K600CF672C-9 is in stock in limited quantities at multiple secondary-market distributors as of 2026-09-08. Heisener lists approximately 5,952 pieces available for immediate shipment; Sierra IC and Vyrian also list the part with quote-based availability. Because this is an obsolete Altera APEX 20KC device, stock levels fluctuate frequently and engineers are advised to lock in supply early and consider second-source qualification of a Cyclone-series alternative.

EP20K600CF672C-9 vs Cyclone III EP3C120F780 - which is better for new designs?

For new designs in 2026, the Cyclone III EP3C120F780 is generally a better choice than the obsolete EP20K600CF672C-9 because it offers a finer process node, lower core voltage, modern Quartus tool support, and active lifecycle status. The APEX 20KC remains viable only for sustaining legacy designs where PCBs are already laid out and firmware is already ported to the APEX architecture. According to Intel FPGA's product migration notes, APEX 20KC designs are not pin-compatible with Cyclone III and require full PCB redesign.

When should I choose EP20K600CF672C-9 over a modern FPGA?

The EP20K600CF672C-9 should be chosen only when sustaining a legacy design whose PCB and firmware are already locked to the APEX 20KC architecture and where a full redesign to a Cyclone-series FPGA is not economically justified. According to Intel FPGA's product migration documentation, modern alternatives are not drop-in compatible, so any swap requires board rework. For new designs, the obsolete lifecycle status of the EP20K600CF672C-9 is a strong reason to start on a Cyclone IV / Cyclone V device instead.

What is the best drop-in replacement for EP20K600CF672C-9?

The best drop-in replacement for the EP20K600CF672C-9 is a same-package, same-die speed-grade variant such as the EP20K600CF672C-8 (faster speed grade, otherwise identical) or EP20K600CF672C-7 (fastest available speed grade). All three share the 672-ball FBGA footprint, 1.8 V VCCINT, MultiVolt I/O, and 488 user I/Os, so they can be soldered onto the same PCB without modification. Only Quartus timing constraints need to be regenerated for the chosen speed grade.

Can EP20K600CF672C-8 replace EP20K600CF672C-9 without PCB changes?

Yes, the EP20K600CF672C-8 can replace the EP20K600CF672C-9 on the same PCB without board rework. Both parts share the 672-ball FBGA package, identical pinout, identical 600K-gate APEX 20KC die, and identical MultiVolt I/O voltage set. The only differences are speed grade (-8 is faster than -9) and possibly temperature grade; designers must regenerate Quartus timing constraints and verify that downstream timing margins remain valid for the faster part.

Where to download the EP20K600CF672C-9 datasheet PDF?

The official EP20K600CF672C-9 datasheet PDF is hosted at https://alterasemi.com/datasheet/alterasemi/EP20K600CF672C-9.pdf (third-party archive). The original Altera APEX 20KC family datasheet is also available through the Intel FPGA documentation portal under the legacy APEX section. For historical reference, FPGAkey and digchips.com also host APEX 20KC datasheet mirrors; engineers should cite the original Altera/Intel PDF when generating compliance documentation.

Where to find the EP20K600CF672C-9 pinout?

The EP20K600CF672C-9 pinout is documented in the APEX 20KC datasheet's package pinout appendix, which lists all 672 FBGA balls by signal name and bank. For the 488 user I/O pins, the datasheet groups pins by I/O bank and by VCCIO voltage, which is critical for MultiVolt I/O PCB design. Engineers using the part should download both the family datasheet and the per-package pinout file from Altera's documentation archive before laying out the BGA footprint.

What is the key specification engineers should know about EP20K600CF672C-9?

The headline specifications of the EP20K600CF672C-9 are: 600,000 typical gates, 488 user I/Os, 4 PLLs, 1.8 V VCCINT core supply, MultiVolt I/O supporting 1.8 V / 2.5 V / 3.3 V / 5.0 V, 672-ball FBGA package, and obsolete lifecycle status. According to the APEX 20KC datasheet, the device also integrates embedded system blocks for RAM/ROM and supports in-system programmability via EPC16 / EPC8 / EPC4 / EPC2 / EPC1 configuration devices. Engineers should treat the obsolete lifecycle as the most important design-time constraint.

エンジニアリング参考データ: EP20K600CF672C-9 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP20K600CF672C-9 when sustaining a legacy design whose PCB and firmware are locked to the APEX 20KC architecture and where the 600K-gate capacity plus 488 MultiVolt I/Os (including 5.0 V tolerance) are required. For timing-margin improvements, select EP20K600CF672C-8 (faster speed grade) on the same PCB. For longest-running APEX 20KC designs that need best-case performance, select EP20K600CF672C-7 (fastest). For new designs in 2026, prefer an active-lifecycle Cyclone IV / Cyclone V / Cyclone 10 LP FPGA instead, since APEX 20KC parts are obsolete and not pin-compatible with Cyclone. All same-package APEX 20KC 672-FBGA variants share the same PCB footprint, enabling drop-in migration between speed grades and package options (CF vs CB).

代替品との比較

パラメータ	この製品	EP20K600CF672C-8	EP20K600CF672C-7	EP20K600CF672C-7ES	EP20K600CF672	EP20K600CF672-3	EP20K600CB672C7
Package	672-ball FBGA (CF suffix, 45x45 mm, 1.27 mm pitch)	672-ball FBGA (CF suffix) - identical	672-ball FBGA (CF suffix) - identical	672-ball FBGA (CF suffix) - identical	672-ball FBGA (CF suffix) - identical	672-ball FBGA (CF suffix) - identical	672-ball BGA (CB suffix) - same ball count
Brand	Altera (now Intel FPGA)	Altera (now Intel FPGA)	Altera (now Intel FPGA)	Altera (now Intel FPGA)	Altera (now Intel FPGA)	Altera (now Intel FPGA)	Altera (now Intel FPGA)
Speed Grade	-9 (mid-tier)	-8 (faster than -9)	-7 (fastest)	-7 (fastest, ES screening)	unsuffixed (no speed bin)	-3 (slower than -9)	-7 (fastest)
Typical Gate Count	600,000 gates	600,000 gates	600,000 gates	600,000 gates	600,000 gates	600,000 gates	600,000 gates
User I/Os	488	488	488	488	488	488	488
Core Voltage (VCCINT)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
MultiVolt I/O (VCCIO)	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V	1.8 V / 2.5 V / 3.3 V / 5.0 V
PLLs	4	4	4	4	4	4	4
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete
Process Node	0.15 µm all-layer copper	0.15 µm all-layer copper	0.15 µm all-layer copper	0.15 µm all-layer copper	0.15 µm all-layer copper	0.15 µm all-layer copper	0.15 µm all-layer copper

主な差別化要因

Drop-in compatible with same-package APEX 20KC variants （vs EP20K600CF672C-8)
MultiVolt I/O supports 1.8 V to 5.0 V on a single die （vs Cyclone III EP3C120F780)
488 user I/Os in a single BGA package （vs EP20K400CFC672-9 (smaller APEX 20KC die))

設計ノート

EP20K600CF672C-9 requires three independent supply rails per the APEX 20KC datasheet: VCCINT = 1.8 V for core logic, VCCIO = 1.8 V / 2.5 V / 3.3 V / 5.0 V per bank, and VCCPD to power the configuration logic. All three rails must be ramped cleanly before configuration begins; otherwise the device may enter an undefined state or fail to configure from the EPC16/EPC8/EPC4/EPC2/EPC1 serial ROM. Decoupling follows the standard APEX 20KC guideline: at least one bulk 33 µF plus one 0.1 µF ceramic per VCCIO bank and a similar network on VCCINT and VCCPD. Place the bulk capacitor as close as physically possible to the BGA's power pins.

The 672-ball FBGA package at 1.27 mm pitch requires via-in-pad or dog-bone fan-out to route signals out of the BGA field. Per Altera's BGA layout guidelines, maintain at least 1.0 mm clearance between vias and use 0.2 mm trace/space for inner escape layers. The 45 × 45 mm package body consumes significant PCB real estate, so plan board stack-up and keep-out zones early. For high-speed LVDS or DDR memory interfaces, use matched-length routing within the bank and keep reference planes continuous under the BGA to maintain signal integrity.

Do not assume the EP20K600CF672C-9 can be hot-swapped onto a board designed for a different APEX 20KC speed grade without regenerating Quartus timing constraints - propagation delay and timing margins vary by speed grade. Also, do not assume any Altera/Intel FPGA in a 672-ball package is pin-compatible; APEX 20KC, Cyclone, and Stratix families share the ball count but have different pin assignments. Finally, verify date-code and RoHS/REACH compliance when sourcing from secondary-market distributors, since original APEX 20KC material may predate RoHS transitions.

Decoupling for the EP20K600CF672C-9 should follow the APEX 20KC datasheet's reference placement: bulk capacitors on each VCCIO bank plus one 0.1 µF ceramic per quadrant of the BGA. The four PLL analog supply pins should be filtered with a ferrite bead and decoupled with a 0.1 µF ceramic plus a 10 µF tantalum or polymer cap. Keep PLL analog supplies quiet and isolated from switching I/O; Altera recommends routing PLL VCC traces over a continuous ground plane. JTAG and configuration pins (TCK, TMS, TDI, TDO, nSTATUS, nCONFIG, CONF_DONE) must be pulled to known states per the configuration scheme.

コンプライアンス情報

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Unknown

ハロゲンフリー

Unknown

紛争鉱物

Unknown

Compliance status not stated in the verified web data. APEX 20KC parts are obsolete; original material may predate RoHS transitions. RoHS, REACH, lead-free, halogen-free, and conflict-minerals compliance should be confirmed per lot date code when sourcing from secondary-market distributors.

データ検証日: 2026-09-08 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

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