EP2C70F672C6N - Cyclone II FPGA, 68K LE, 672-BGA | Intel/Altera
部品番号: EP2C70F672C6N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $409.71 | $409.71 |
| 10 | $365.5 | $3,655.00 |
| 100 | $312.4 | $31,240.00 |
| 250 | $285.2 | $71,300.00 |
| 500 | $260.8 | $130,400.00 |
EP2C70F672C6N 概要
An FPGA (Field-Programmable Gate Array) is a programmable semiconductor device built from an array of configurable logic blocks (LABs), programmable interconnect, embedded memory, and hard IP such as PLLs and multipliers, all governed by SRAM-based configuration memory. Within the broader semiconductor taxonomy, FPGAs sit between fixed-function ASICs and software-driven microprocessors, delivering hardware-timed parallelism with in-field reconfigurability. The Cyclone II family targets low-cost, high-volume applications using a 90 nm CMOS process, optimizing logic density per dollar.
Key features include 4,276 logic array blocks (LABs), 150 embedded 18x18 multipliers for DSP workloads, and four phase-locked loops (PLLs) for clock synthesis and skew management. The 1,152,000-bit embedded memory is organized in M4K blocks supporting true dual-port, single-port, and FIFO operation modes. The device drives LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards through 422 user I/O pins distributed across eight I/O banks, enabling mixed-voltage interfacing with DDR/DDR2 memories, microprocessors, and high-speed peripherals.
Cyclone II architecture is implemented on a 90 nm low-k dielectric CMOS process with copper interconnect, balancing static power, dynamic performance, and density. Internal configuration is stored in SRAM and loaded from external flash or a configuration controller, supporting in-field updates and rapid design iteration. The 672-ball FineLine BGA package with 1.0 mm ball pitch provides full I/O utilization while remaining manageable with conventional PCB fanout techniques.
Typical applications include industrial motor control, video processing pipelines, low-cost protocol bridging, embedded vision, telecom line cards, and education or hobby prototyping boards. The combination of embedded 18x18 multipliers and significant logic density supports DSP tasks such as FIR filtering and image preprocessing without external DSP devices.
When designing with the EP2C70F672C6N, decide the configuration scheme (AS or JTAG) and clock distribution before PCB layout; the 672-BGA package requires careful fanout with microvia or via-in-pad on lower-layer boards. Decoupling and power estimation must follow the Cyclone II Device Handbook because dynamic power of 68K LEs plus SRAM configuration memory dominates thermal budgeting.
This page synthesizes distributor pricing, Cyclone II drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone - useful for both new designs and legacy EOL substitution.
ドロップイン代替品: EP2C70F672C6N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2C70F672C6N （同一形状・フットプリント） — 相違点: Package, Speed Grade, RoHS Status, Family, Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EP2C70F672C7N
✅ ドロップイン✓ 在庫あり
$195 / 個
データシートを見る →EP2C70F672C8
✅ ドロップイン✓ 在庫あり
$238.2 / 個
データシートを見る →EP2C70F672C6
✅ ドロップイン✓ 在庫あり
$338.91 / 個
データシートを見る →EP2C70F672I6N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP2C70F672C7N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$195 / 個
データシートを見る →EP2C70F672C6N 最大定格＆電気的特性
| Family | Cyclone II |
| Series | EP2C70 |
| Logic Elements | 68,416 |
| Logic Array Blocks (LABs) | 4,276 |
| Total RAM Bits | 1,152,000 |
| Embedded 18x18 Multipliers | 150 |
| PLLs | 4 |
| Maximum User I/O | 422 |
| I/O Banks | 8 |
| パッケージ | 672-ball FBGA, 27x27 mm, 1.0 mm pitch |
| Speed Grade | C6 |
| 動作温度 | 0C to +85C (commercial) |
| Process Technology | 90 nm low-k CMOS, copper interconnect |
| Configuration Memory | SRAM (volatile) |
| Configuration Schemes | AS, AP, PS, JTAG |
| Supported I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| 実装タイプ | Surface Mount (BGA) |
| RoHS ステータス | Lead-free (per FBGA marking) |
EP2C70F672C6N 672-ball fbga, 27x27 mm, 1.0 mm pitch ピン配置ガイド
EP2C70F672C6N (672-ball fbga, 27x27 mm, 1.0 mm pitch パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2C70F672C6N.
詳細は データシート をご参照ください。
主な用途
EP2C70F672C6N の用途: 6 件s: Industrial Motor Control, Video Processing Pipeline, Low-Cost Protocol Bridging, Embedded Vision Preprocessing, Telecom Line Card Glue Logic, Education and Hobby Prototyping.
Industrial Motor Control
The EP2C70F672C6N suits industrial motor control drives where the 150 embedded 18x18 multipliers implement Field-Oriented Control (FOC) and Space Vector PWM datapaths with hardware-timed determinism. The 68,416 LEs absorb encoder interfaces, current-loop PI controllers, and protection logic, while four PLLs synthesize the switching-frequency clock from a low-frequency reference. The 672-FBGA package supports the wide 0C to +85C commercial range typical of cabinet-mounted drives with forced-air cooling.
おすすめ
Video Processing Pipeline
The EP2C70F672C6N handles entry-level video processing such as scaling, deinterlacing, and color-space conversion at standard-definition and lower HD resolutions. The 1,152,000 bits of embedded M4K memory provide line buffers and frame-delay storage, while the 150 multipliers accelerate 2D filter operations. Designers target the C6 speed grade for power-efficient 1080i processing, and the eight I/O banks carry parallel video buses plus DDR2 frame buffers.
おすすめ
Low-Cost Protocol Bridging
The EP2C70F672C6N bridges industrial and networking protocols such as UART-to-SPI, I2C-to-parallel, or custom bus conversion where the 422 user I/Os connect to multiple heterogeneous peripherals simultaneously. The 68,416 LEs implement state machines and FIFOs for protocol conversion without external logic, while the LVDS-capable I/Os drive backplanes up to several hundred megabits per second. The 672-FBGA footprint suits multi-protocol industrial gateways that must accept many connectors.
おすすめ
Embedded Vision Preprocessing
The EP2C70F672C6N performs edge-detection, thresholding, and histogram preprocessing at the sensor side of an embedded camera or scanner, offloading these tasks from the host CPU. The 150 18x18 multipliers accelerate convolution kernels, while M4K blocks store kernel coefficients and line memories. The 672-FBGA package supports up to 422 I/Os for parallel sensor interfaces, plus DDR2 frame buffers for downstream consumer SoCs.
おすすめ
Telecom Line Card Glue Logic
The EP2C70F672C6N provides glue-logic integration on telecom line cards where TDM, HDLC, or custom serial protocols require hardware-timed serialization and framing. The 422 user I/Os aggregate multiple low-speed serial links, and four PLLs derive framing references from system clocks. The 672-FBGA package fits behind backplane connectors with 1.0 mm pitch, which can fan out into 8 I/O banks carrying LVDS or HSTL to adjacent ASICs.
おすすめ
Education and Hobby Prototyping
The EP2C70F672C6N serves as the main FPGA on university laboratory boards and hobby development kits because the 68K LE capacity lets students run complete RISC-V soft cores plus peripherals on a single chip. The 672-FBGA footprint is large enough to break out dozens of LEDs, switches, and connectors, while the commercial temperature range fits classroom environments. Quartus II Web Edition supports the part free of charge for academic and hobby use.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2C70F672C6N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2C70F672C7N | EP2C70F672C8 | EP2C70F672C6 | EP2C70F672I6N | EP2C70F672C7N (lead-free) |
|---|---|---|---|---|---|---|
| Package | 672-FBGA (27x27 mm, 1.0 mm pitch) | 672-FBGA (27x27 mm, 1.0 mm pitch) - same | 672-FBGA (27x27 mm, 1.0 mm pitch) - same | 672-FBGA (27x27 mm, 1.0 mm pitch) - same | 672-FBGA (27x27 mm, 1.0 mm pitch) - same | 672-FBGA (27x27 mm, 1.0 mm pitch) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 |
| Embedded RAM Bits | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 |
| Maximum User I/O | 422 | 422 | 422 | 422 | 422 | 422 |
| Speed Grade | C6 | C7 (faster) | C8 (slower) | C6 (same) | C6 industrial temp | C7 Pb-free |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C |
| Lead-Free / RoHS | Lead-free (FBGA marking) | Lead-free | Lead-free | Lead (pre-RoHS tray variant) | Lead-free | Lead-free (Pb-free) |
主な差別化要因
- 68K LEs in a commercial-grade Cyclone II family part with 6 second internal clock domains （vs EP2C70F672C7N)
- Identical die and pinout to industrial-temp variant （vs EP2C70F672I6N)
- Largest non-transceiver Cyclone II device with 4 PLLs and 150 multipliers （vs EP2C70F672C8)
設計ノート
The 672-FBGA package uses a 1.0 mm ball pitch on a 27x27 mm body, which is at the practical limit of conventional 4-layer PCB fanout with 4 mil trace/space. For dense routing, plan at least 6 layers or adopt microvia (laser-drilled) stackup on the top two layers to escape the inner-row balls. Reference the Cyclone II Device Handbook pin connection guidelines for VCCINT, VCCA, VCCIO, and GND ball assignments before committing the stackup.
Estimated: at typical utilization of 70 percent logic toggling at 100 MHz on 68K LEs plus 4 PLLs and DDR2 interface active, ICCINT draws 1.0 to 1.5 A from a 1.2 V rail. The eight VCCIO banks each carry separate supplies so mixed-voltage interfaces (LVDS/LVCMOS/SSTL) require 4-5 LDO outputs. Decouple each VCCINT ball with a 0.1 uF X7R plus a 10 uF bulk capacitor placed within 100 mil of the ball, per the Cyclone II handbook decoupling diagram.
Do not reuse a Cyclone IV E PCB layout for the Cyclone II EP2C70F672C6N: the 672-FBGA ball maps differ between the two families even though pin count matches. Always verify the specific ordering code's pinout file in Quartus II Pin Planner before sign-off. SRAM-based configuration means the device loses its bitstream on power-down; if the application requires non-volatile configuration, pair the FPGA with an EPCS16/EPCS64 configuration flash.
コンプライアンス情報
Lead-free per FBGA part marking per DigiKey listing. AEC-Q100 not applicable for non-automotive commercial/industrial FPGA. REACH and conflict-mineral data not present in verified sources.
