EP2S90F1020I3N - 90K LE Stratix II FPGA 1.2V FC-FBGA-1020 | Altera
部品番号: EP2S90F1020I3N ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EP2S90F1020I3N 概要
A Field-Programmable Gate Array (FPGA) is a type of programmable logic IC that contains an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and programmable interconnect. Stratix II specifically introduced an adaptive logic module (ALM) architecture, walking the taxonomy of: FPGA -> programmable logic -> ASIC-prototype silicon -> semiconductor. Its place in the system hierarchy is as a flexible hardware accelerator that bridges the gap between fixed-function ASICs and software-only solutions running on general-purpose processors.
Key features of the EP2S90F1020I3N include up to 12 embedded DSP blocks capable of 9-bit x 9-bit multipliers, dedicated high-speed serial transceivers supporting source-synchronous interfaces, embedded TriMatrix memory with true dual-port RAM configurations, and an enhanced routing architecture with reduced congestion versus the original Stratix. The 1.2 V core and 90 nm process keep dynamic power within practical limits while still supporting DSP workloads above 250 MHz in typical pipelined designs.
The Stratix II architecture adopts a DirectDrive multiplexers-based ALM that doubles the effective logic capacity per area versus the first-generation Stratix. The 1020-pin FC-FBGA package provides ample signal margin for parallel external memory interfaces (DDR/DDR2 SDRAM controllers, QDR SRAM) and source-synchronous LVDS links. The I3 speed grade is the third-fastest in the Stratix II lineup, balancing timing margin against cost.
Typical applications include ASIC prototyping and emulation, high-end communications protocol bridging, high-performance DSP filter banks, video and image processing pipelines, and military/aerospace signal processing. The wide embedded memory and DSP density also suit radar and beam-forming front-ends, software-defined radio baseband, and complex state-machine controllers in industrial automation.
When designing with the EP2S90F1020I3N, plan a 12-layer PCB stack-up with continuous VCCINT and GND planes to control simultaneous-switching noise on the 1020-ball BGA, and provide at least eight 0.1 uF plus four 10 uF decoupling capacitors within 200 mils of the package. The Flip-Chip BGA also requires precise reflow profiling and X-ray inspection after assembly.
This page consolidates distributor stock, parametric cross-checks, and Altera/Intel Stratix II family alternatives not found in any single datasheet - a one-stop source for engineers evaluating or sourcing this legacy high-density FPGA.
ドロップイン代替品: EP2S90F1020I3N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2S90F1020I3N （同一形状・フットプリント） — 相違点: Package, Speed Grade, Operating Temperature, Mounting Type, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EP2S90F1020I3
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP2S90F1020C3N
✅ ドロップイン✓ 在庫あり
$1995 / 個
データシートを見る →EP2S90F1020C4N
✅ ドロップイン✓ 在庫あり
$1320 / 個
データシートを見る →EP2S90F1020C5N
✅ ドロップイン✓ 在庫あり
$1240 / 個
データシートを見る →EP2S90F1020I4N
✅ ドロップイン✓ 在庫あり
$1995 / 個
データシートを見る →EP2S90F1020I3N 最大定格＆電気的特性
| Family | Stratix II |
| Logic Elements (LEs) | 90,960 |
| Embedded Memory Bits | 4,520,488 |
| Embedded DSP Blocks | 12 (9-bit x 9-bit multiplier support) |
| Process Technology | 90 nm |
| Core Supply Voltage (VCCINT) | 1.2 V |
| Maximum Internal Frequency | 816.99 MHz (per datasheet headline) |
| Speed Grade | I3 (industrial temperature range) |
| パッケージ | 1020-ball FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Pin/Ball Count | 1020 |
| 動作接合温度 | -40C to +100C (industrial, per I3 suffix) |
| 実装タイプ | Surface Mount (BGA) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
EP2S90F1020I3N 1020-ball fc-fbga (flip-chip fine-pitch bga) ピン配置ガイド
EP2S90F1020I3N (1020-ball fc-fbga (flip-chip fine-pitch bga) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2S90F1020I3N.
詳細は データシート をご参照ください。
主な用途
EP2S90F1020I3N の用途: 6 件s: ASIC Prototyping and Emulation, High-Speed DSP Pipeline, High-Throughput Video and Image Processing, Industrial Automation and Control, Communications Protocol Bridging, Aerospace and Defense Signal Processing.
ASIC Prototyping and Emulation
The EP2S90F1020I3N's 90,960 logic elements and 4,520,488 embedded RAM bits make it a strong fit for ASIC prototyping and in-circuit emulation, where multiple million-gate ASICs are partitioned into a single FPGA fabric. Its 1020-ball FC-FBGA package exposes sufficient user I/O to map wide ASIC buses, and the TriMatrix memory blocks deliver true dual-port RAM for transaction-level models. Compared with smaller Stratix II parts (EP2S30/60), the EP2S90 reduces multi-FPGA partitioning glue logic by ~30%, simplifying timing closure in Quartus II.
おすすめ
High-Speed DSP Pipeline
With 12 embedded DSP blocks capable of 9-bit x 9-bit multiplications at hundreds of MHz, the EP2S90F1020I3N powers FIR filter banks, FFT engines, and channelizer pipelines in radar and software-defined radio baseband. The 816.99 MHz fabric Fmax lets designers pipeline 256-tap FIR filters at >200 MHz clock, while 4.5 Mbits of TriMatrix memory holds tap coefficients and rotating buffers. Industrial -40C to +100C junction support means the same device serves outdoor basestation and shipboard installations.
おすすめ
High-Throughput Video and Image Processing
The EP2S90F1020I3N's combination of 4.5 Mbits embedded RAM, parallel LVDS pairs, and 1020-ball FC-FBGA I/O is well suited to multi-channel HD-SDI video processing, image preprocessing for machine vision, and real-time motion analysis pipelines. Wide internal data paths and DDR2 external memory controllers allow frame-buffer storage without external SRAM. Compared with smaller Cyclone-series FPGAs, the EP2S90 absorbs entire processing chains on a single die, eliminating inter-chip synchronization.
おすすめ
Industrial Automation and Control
Industrial -40C to +100C junction rating and 90 nm low-power process make the EP2S90F1020I3N viable for factory-floor controllers, motor drives, and deterministic real-time control loops. Embedded TriMatrix RAM supports deterministic-cycle register banks for safety PLC code, while 12 DSP blocks accelerate field-oriented control (FOC) math for multi-axis servos. The 1020-ball BGA's high pin count also accommodates parallel industrial buses (PROFIBUS, EtherCAT slave PHY links) and abundant GPIO for sensor fusion.
おすすめ
Communications Protocol Bridging
The EP2S90F1020I3N's high user-I/O count and source-synchronous LVDS support enable bridging between telecom protocols such as SONET/SDH, OTN, and proprietary backplane fabrics. The 4.5 Mbit embedded memory absorbs packet buffers for line-card aggregation, and the 90 nm process keeps dynamic power within telecom thermal envelopes. Compared with discrete protocol bridges, a single EP2S90 device can re-route 8+ simultaneous channels with sub-microsecond latency.
おすすめ
Aerospace and Defense Signal Processing
The industrial -40C to +100C temperature window of the EP2S90F1020I3N matches MIL-STD-810 environmental profiles for radar, electronic-warfare, and avionics signal processing subsystems. 12 hardened DSP blocks and 4.5 Mbits of true dual-port RAM handle pulse-compression, beam-forming, and I/Q demodulation at real-time rates. Designers typically pair the EP2S90 with external ADC/DAC companions for RF front-end digitisation, leveraging the 1020-ball FC-FBGA for parallel LVDS data lanes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2S90F1020I3N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2S90F1020C3N | EP2S90F1020C4N | EP2S90F1020C5N | EP2S90F1020I4N | EP2S90F1020I3 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 1020-ball FC-FBGA | 1020-ball FC-FBGA - same | 1020-ball FC-FBGA - same | 1020-ball FC-FBGA - same | 1020-ball FC-FBGA - same | 1020-ball FC-FBGA - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Embedded Memory Bits | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 |
| Speed Grade | I3 (industrial) | C3 (commercial, slower ~10-15%) | C4 (commercial, slower ~20%) | C5 (commercial, slowest) | I4 (industrial, slower ~10%) | I3 (industrial, identical) |
| Operating Junction Temperature | -40C to +100C | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | -40C to +100C (industrial) |
| Process Node | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Core Voltage (VCCINT) | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Lifecycle Status | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy |
主な差別化要因
- Highest-density Stratix II with industrial temperature grade （vs EP2S60F1020C5N)
- Faster speed grade at industrial temperature （vs EP2S90F1020I4N)
- Lead-free RoHS compliance （vs EP2S90F1020I3)
設計ノート
The 1020-ball Flip-Chip FC-FBGA demands an advanced PCB stack-up of at least 12 layers with continuous VCCINT and GND planes to control simultaneous-switching noise (SSN) on the 90 nm fabric. Place eight 0.1 uF X7R decoupling capacitors plus four 10 uF bulk capacitors within 200 mils of the package, and route differential pairs with matched length within 5 mils. X-ray inspection post-reflow is mandatory for flip-chip BGA - optical AOI cannot reliably detect opens under the flip-chip die.
Stratix II EP2S90 power sequencing requires VCCINT (1.2 V) to ramp before VCCIO (typically 2.5/3.3 V), with VCCAUX and VCCPD following per Altera's recommended sequence. Reverse or simultaneous ramp can prevent successful configuration or trigger long-term reliability stress on the configuration cell array. Use a multi-rail sequencer such as Altera's Power-Tree Reference Design and verify ramp slopes with a 4-channel scope before first power-up.
Configuration bitstream loading through JTAG or AS (active serial) requires the configuration flash (EPCS) voltage to match VCCIO bank voltage - mismatched flash voltage is the most common bring-up failure. Also confirm the Quartus II pin assignment (.qsf) matches the PCB BGA ball map: even a single swapped ball on the 1020-pin FC-FBGA can corrupt JTAG IDCODE reads. Always run Quartus II pin-check before fab.
Estimated: at full utilization (90,960 LEs @ 200 MHz, 12 DSP blocks active), the EP2S90F1020I3N dissipates approximately 8-12 W on the 90 nm process. With the FC-FBGA exposed-die top surface, attach a heatsink or thermal-interface material rated for flip-chip BGA. Junction-to-ambient theta_JA is typically 15-20 C/W with a 400 LFM airflow, giving ~160 C junction rise at 10 W - near the +100C industrial limit. Add a thermistor for shutdown protection.
コンプライアンス情報
RoHS compliance indicated by 'N' suffix on MPN per Altera/Intel part-number convention. AEC-Q100 not applicable - this is a high-density FPGA, not an automotive-qualified IC. Reach compliance assumed per standard Altera product compliance. Halogen-free status not explicitly stated in the verified web data and is marked as needed.
