EP2S90F1020I4GA - 90K LEs Stratix II FPGA, 758 I/O FBGA-1020 | Intel
部品番号: EP2S90F1020I4GA ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $320 | $320.00 |
| 10 | $295 | $2,950.00 |
| 100 | $265 | $26,500.00 |
| 500 | $240 | $120,000.00 |
| 1,000 | $220 | $220,000.00 |
EP2S90F1020I4GA 概要
A Field Programmable Gate Array (FPGA) is a semiconductor device containing a matrix of configurable logic blocks (CLBs), programmable interconnect, and dedicated hardware blocks such as block RAM, DSP slices, and high-speed transceivers. Designers describe logic using HDL (Verilog or VHDL) and synthesize it onto the FPGA fabric, allowing rapid iteration versus ASIC development. FPGAs sit hierarchically between general-purpose microcontrollers and ASICs, offering higher performance-per-watt than CPUs for parallel workloads while preserving reprogrammability. The Stratix II family extends this to ASIC-prototyping and signal-processing designs with embedded multipliers and substantial block RAM.
Key features of the EP2S90 include up to 758 user I/O pins via the FBGA-1020 package, four enhanced phase-locked loops (PLLs) for clock management, support for external memory interfaces including DDR/DDR2/QDRII, and configuration via passive serial, fast passive parallel, or JTAG modes. The 'GA' suffix on the part number indicates the specific package and lead-free/RoHS designation as used by Altera/Intel ordering codes. The I4 speed grade places this part in the mid-performance Stratix II tier.
Architecturally, the Stratix II device uses an ALM-based logic structure with adaptive look-up tables, dedicated carry chains, and on-chip memory distributed across M512, M4K, and M-RAM blocks. The embedded DSP blocks implement 18x18 multipliers with optional accumulation and pre-adders, ideal for FIR filters and FFTs in wireless baseband and video processing pipelines.
Typical applications include ASIC prototyping, high-speed digital signal processing, telecom line cards, test and measurement equipment, and high-performance industrial control. When designing with this part, plan power sequencing carefully: the Stratix II requires multiple supply rails (VCCINT, VCCA, VCCIO, VCCPD) with monotonic ramp requirements and a specific POR (power-on-reset) sequence to avoid configuration failure.
ドロップイン代替品: EP2S90F1020I4GA — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2S90F1020I4GA （同一形状・フットプリント） — 相違点: Package, Speed Grade, Operating Temperature, Mounting Type, Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EP2S90F1020I4
✅ ドロップイン✓ 在庫あり
$2200 / 個
データシートを見る →EP2S90F1020I3N
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EP2S90F1020C5N
✅ ドロップイン✓ 在庫あり
$1240 / 個
データシートを見る →EP2S90F1020C4N
✅ ドロップイン✓ 在庫あり
$1320 / 個
データシートを見る →EP2S90F1020C3N
✅ ドロップイン✓ 在庫あり
$1995 / 個
データシートを見る →EP2S90F1020I4GA 最大定格＆電気的特性
| Family | Stratix II |
| Logic Elements (LEs) | 90,960 |
| Embedded Memory | 4,520,488 bits (approximately 4.4 Mbit) |
| Embedded 18x18 Multipliers | 192 |
| Maximum User I/O | 758 |
| Process Technology | 90 nm CMOS |
| パッケージ | 1020-ball FC-FBGA |
| 動作温度 | -40C to +100C (industrial) |
| Speed Grade | I4 (mid-performance, industrial) |
| Supply Voltage - Core (VCCINT) | 1.2 V nominal |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs | 4 enhanced PLLs |
| External Memory Support | DDR, DDR2, QDRII, SDR |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Program Memory Type | SRAM (volatile, requires configuration device) |
EP2S90F1020I4GA 1020-ball fc-fbga ピン配置ガイド
EP2S90F1020I4GA (1020-ball fc-fbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2S90F1020I4GA.
詳細は データシート をご参照ください。
主な用途
EP2S90F1020I4GA の用途: 6 件s: ASIC Prototyping, High-Speed Digital Signal Processing, Telecom Line Cards, Test and Measurement Instrumentation, Industrial Control and Automation, Military and Aerospace (Legacy Designs).
ASIC Prototyping
The EP2S90F1020I4GA's 90,960 LEs and 1020-pin FBGA package make it an ideal ASIC prototyping platform. Engineers map RTL designs onto the Stratix II fabric and validate functionality at near-ASIC speeds before committing to fabrication. With 192 DSP blocks and 4.4 Mbit embedded RAM, complex SoCs can be emulated including processor cores, peripherals, and glue logic. The I4 industrial speed grade supports clock rates up to several hundred MHz, sufficient for most pre-silicon validation scenarios.
おすすめ
High-Speed Digital Signal Processing
The EP2S90F1020I4GA's 192 18x18 hardware multipliers deliver up to ~76 GMACs of DSP throughput, enabling real-time FFTs, FIR filters, and baseband processing. The block RAM supports dual-port operation ideal for sample buffering in radar and software-defined radio pipelines. Combined with 4 PLLs for flexible clock synthesis, this FPGA implements complete digital receivers on a single chip, reducing BOM cost versus discrete DSP + memory architectures in test & measurement equipment.
おすすめ
Telecom Line Cards
Stratix II FPGAs like the EP2S90F1020I4GA have been widely deployed in telecom line cards for packet processing, SERDES aggregation, and protocol bridging. The 758 user I/O pins support wide parallel backplanes, while external memory interfaces handle DDR/DDR2/QDRII for deep packet buffers. Industrial temperature grade and high logic density make this part suitable for central-office equipment requiring long-life-cycle support and field-proven reliability.
おすすめ
Test and Measurement Instrumentation
In oscilloscopes, logic analyzers, and protocol analyzers, the EP2S90F1020I4GA provides the parallel processing horsepower to capture and process high-speed signals in real time. The 90,960 LEs support complex trigger state machines, while 758 I/O pins interface directly with high-bandwidth ADCs and DACs. Industrial temperature grade ensures stable operation in lab and field environments, and SRAM-based configuration allows field firmware updates as new protocols emerge.
おすすめ
Industrial Control and Automation
Programmable logic controllers (PLCs) and motion controllers benefit from the EP2S90F1020I4GA's high I/O count (758 pins) for parallel sensor/actuator interfaces and 192 DSP blocks for real-time servo-loop computation. The industrial -40C to +100C operating range supports deployment in factory floors, outdoor enclosures, and ruggedized mobile equipment. Deterministic SRAM-based configuration enables secure boot for safety-critical industrial applications.
おすすめ
Military and Aerospace (Legacy Designs)
Established Stratix II designs in defense and aerospace systems continue to use the EP2S90F1020I4GA due to its long product life cycle, industrial temperature range, and mature toolchain support. Its 90,960 LEs handle sensor fusion, video processing, and secure communications payloads. Designers specify this part for legacy programs where re-validation of newer FPGAs would be cost-prohibitive and where the high pin-count FBGA-1020 package integrates seamlessly into existing board layouts.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2S90F1020I4GA — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2S90F1020I4 | EP2S90F1020I3N | EP2S90F1020C5N | EP2S90F1020C4N | EP2S90F1020C3N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1020-ball FC-FBGA | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) |
| Logic Elements (LEs) | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | I4 | I4 | I3 (slower) | C5 (faster, commercial) | C4 (equivalent, commercial) | C3 (slower, commercial) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Commercial (0 to 85C) | Commercial (0 to 85C) | Commercial (0 to 85C) |
| Embedded Multipliers (18x18) | 192 | 192 | 192 | 192 | 192 | 192 |
| User I/O Pins | 758 | 758 | 758 | 758 | 758 | 758 |
| RoHS / Lead-Free | Yes (GA suffix) | Yes | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) |
主な差別化要因
- Identical silicon and footprint across I/C speed grades （vs EP2S90F1020C5N (faster commercial speed grade))
- Higher logic density than Stratix II EP2S60 （vs EP2S60F1020I4 (60K LE on same FBGA-1020 package))
- GA suffix ensures RoHS compliance orderability （vs EP2S90F1020I4 (bare MPN without GA suffix))
設計ノート
The EP2S90F1020I4GA requires four supply rails: VCCINT (1.2 V core), VCCA (analog PLL 1.2 V), VCCIO (1.2 V to 3.3 V per bank), and VCCPD (2.5 V or 3.3 V pre-driver). Stricter ramp-ordering rules apply: VCCINT must precede VCCPD and VCCIO during power-up; consult Stratix II handbook Figure 5-1. Recommended: use a dedicated power management IC with monotonic ramp and minimum 1 ms rise time. Estimated: at full utilization (90,960 LEs switching at 50% toggle rate, 250 MHz) the core current exceeds 3 A; design the VCCINT plane with at least 2 oz copper or 4+ vias per decoupling capacitor.
Estimated: at worst case (1.2 V * 3 A core + I/O bank activity), the EP2S90F1020I4GA can dissipate 5-8 W. The 1020-ball FC-FBGA package has a junction-to-ambient thermal resistance theta_JA of approximately 12-15 C/W with a 4-layer PCB thermal via array under the die. For continuous industrial-temperature operation, an embedded heat spreader or forced airflow is recommended when ambient exceeds 70C. Use the Quartus PowerPlay analyzer to estimate dynamic power per design and derate accordingly.
The 1020-ball FC-FBGA uses a 1.0 mm ball pitch. PCB design must use laser-drilled microvias or stacked-via construction; standard 8-mil vias will not fan-out correctly. Assign at least one full PCB ground plane directly under the BGA for return-current management, and stitch all four power planes with 0.1 uF decoupling capacitors at every VCCIO bank boundary. Place the EPCS configuration memory within 2 inches of the FPGA with controlled-impedance routing for the DATA, DCLK, and nCS signals.
Do not confuse Stratix II (this part, 90 nm) with Stratix II GX (which has transceivers) or Stratix III/IV/V (different pinouts, packages, and voltages). Verify configuration mode strapping (MSEL pins) match the boot source - incorrect MSEL settings cause configuration failure. The 'GA' suffix denotes RoHS orderability; the bare MPN may not be lead-free. Last-time-buy status means order cancellation terms are stricter; commit to volumes early to avoid re-sourcing challenges.
コンプライアンス情報
RoHS compliance confirmed via GA suffix per Altera/Intel ordering guide. Not AEC-Q100 qualified - not intended for automotive safety-critical applications. For automotive, select Cyclone IV/V or newer automotive-grade FPGAs.