Intel

EP2S90F780C5N - Stratix II FPGA, 90K LE, 780-FBGA | Intel

部品番号: EP2S90F780C5N ✗ 生産終了

在庫あり 1〜3営業日以内に発送

1.2 V Vdss 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch, lead-free Package 609.76 MHz Speed 4,520,488 Memory

開始価格 $198 USD / 個

MOQ: 1 |

価格更新日: 2026-09-08

ボリューム価格

数量	単価	小計
1	$285	$285.00
10	$268.5	$2,685.00
25	$252	$6,300.00
100	$225	$22,500.00
500	$198	$99,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP2S90F780C5N 概要

The Intel (formerly Altera) EP2S90F780C5N is a high-density Stratix II family Field-Programmable Gate Array (FPGA) with 90,960 logic elements, 4,520,488 bits of embedded memory, and a 1.2 V core supply, housed in a 780-ball FineLine BGA (FBGA) package measuring 29 x 29 mm with 1 mm ball pitch. It is built on a 90 nm CMOS process and operates with an internal frequency up to 609.76 MHz, supporting high-performance digital logic, DSP, and memory-intensive applications.

What is an FPGA? A Field-Programmable Gate Array is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnects, and dedicated silicon resources such as block RAM, DSP blocks, and high-speed transceivers. FPGAs sit above general-purpose microcontrollers in the digital design hierarchy: they can implement arbitrary parallel logic, custom processor cores, hardware accelerators, and high-bandwidth data-path pipelines that an ASIC would otherwise handle, but with the advantage of in-system reprogrammability. The Stratix II family in particular pioneered the adaptive logic module (ALM) architecture, replacing the traditional 4-input LUT with an 8-input fracturable LUT for higher logic efficiency.

Key features of the EP2S90F780C5N include up to 534 user I/O pins, embedded multiplier blocks suitable for DSP, dedicated high-speed serial interfaces, and support for external memory interfaces including DDR, DDR2, QDR, and RLDRAM. The device integrates PLLs for clock management and offers robust configuration options through JTAG, Passive Serial, Fast Passive Parallel, and Active Serial modes.

Architecturally, the Stratix II ALM can implement any 7-input LUT plus a small auxiliary function, dramatically reducing logic-area waste compared to older 4-LUT architectures. TriMatrix embedded memory blocks (M512, M4K, M-RAM) provide distributed RAM, ROM, FIFO, and shift-register functions, while DSP blocks deliver dedicated multiply-accumulate throughput. The 90 nm process, 1.2 V core, and 1.0 V/1.2 V selectable I/O standards balance performance and power.

Typical applications include telecommunications baseband processing, high-speed image and video processing, ASIC prototyping, military and aerospace signal processing, and industrial control systems. With 534 I/O and ~4.5 Mbit of block RAM, the EP2S90F780C5N handles large data-plane buffers and multiple parallel interfaces.

Design consideration: Stratix II devices are now in their mature lifecycle. Designers targeting new designs should verify availability and consider Cyclone IV/V or MAX 10 as modern, lower-cost alternatives where the EP2S90's logic density is not required.

This page synthesizes distributor pricing, drop-in alternatives from the Site MPN list, lifecycle guidance, and practical design notes not consolidated in the manufacturer datasheet alone.

ドロップイン代替品: EP2S90F780C5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP2S90F780C5N （同一形状・フットプリント） — 相違点: Package, RoHS Status, Speed Grade, Operating Temperature, Logic Elements.

EP2S130F780C5

Intel

Package: 780-FBGA (FC-FBGA), 29 mm x 29 mm

Operating Temperature: 0 C to +85 C (TJ)

Logic Elements: 132,540

比較対象 EP2S90F780C5N →

EP2S130F780C5N

Intel

Package: 780-FBGA (29 x 29 mm), 1.0 mm pitch

RoHS Status: Compliant (lead-free FBGA)

Operating Temperature: 0 °C to 85 °C (Commercial)

比較対象 EP2S90F780C5N →

EP2S90F780C4

Intel

Package: 780-ball FBGA (FC-FBGA), 29 mm x 29 mm

RoHS Status: unknown

Speed Grade: C4

比較対象 EP2S90F780C5N →

EP2S90F780C4N

Intel

Package: 780-FBGA (FC-FBGA), 29 x 29 mm, 1 mm pitch

Operating Temperature: 0 °C to 85 °C (commercial)

比較対象 EP2S90F780C5N →

EP2S90F780C5

Altera

RoHS Status: RoHS non-compliant (per alterachips listing)

Operating Temperature: 0 C to 85 C (Commercial)

比較対象 EP2S90F780C5N →

EP2S90F780I4

Intel

Package: FBGA-780 (29 x 29 mm, 1.0 mm pitch)

RoHS Status: Lead-free (per datasheet)

Speed Grade: -4 (I4 suffix)

比較対象 EP2S90F780C5N →

EP2S90F780I4N

Altera

Package: 780-BBGA (FineLine BGA, 29 x 29 mm, 1 mm pitch)

Logic Elements: 90,960 LE

比較対象 EP2S90F780C5N →

EP2S90F780I4NAB

Intel

Package: 780-BGA (29x29 mm)

RoHS Status: Compliant

Speed Grade: I4 (industrial, -4)

比較対象 EP2S90F780C5N →

✅ ドロップイン ⚠️ 仕様未検証

Intel

📦 780-ball FBGA

Stratix II · 132,540 · 6627 · 534 · 6,737,280 · 252 · 90 nm CMOS · 1.15 V to 1.25 V (typ. 1.2 V)

✓ 在庫あり

$2295 / 個

データシートを見る →

EP2S90F780C5N 最大定格＆電気的特性

Family	Stratix II
Logic Elements	90,960
Adaptive Logic Modules (ALMs)	45,960
Embedded Memory Bits	4,520,488
Embedded Multipliers (18x18)	384
Maximum User I/O	534
Process Technology	90 nm CMOS
Core Supply Voltage	1.2 V
Internal Frequency (max)	609.76 MHz
動作温度範囲	0C to 85C (TJ, commercial)
Speed Grade	C5
パッケージ	780-ball FBGA, 29 x 29 mm, 1.0 mm pitch, lead-free
実装タイプ	Surface Mount
Configuration Method	JTAG, Passive Serial, Fast Passive Parallel, Active Serial
RoHS ステータス	Lead-free (per datasheets.com listing)

EP2S90F780C5N 780-ball fbga, 29 x 29 mm, 1.0 mm pitch, lead-free ピン配置ガイド

EP2S90F780C5N (780-ball fbga, 29 x 29 mm, 1.0 mm pitch, lead-free パッケージ) のピン配置。このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

EP2S90F780C5N の 780-ball fbga, 29 x 29 mm, 1.0 mm pitch, lead-free パッケージピン配置図

詳細なピン配置データはありません: EP2S90F780C5N.

詳細はデータシートをご参照ください。

主な用途

EP2S90F780C5N の用途: 6 件s: Telecommunications Baseband Processing, ASIC Prototyping and Emulation, High-Speed Image and Video Processing, Military and Aerospace Signal Processing, Industrial Control and Test Instrumentation, Software-Defined Radio (SDR) Platforms.

🌐

Telecommunications Baseband Processing

The EP2S90F780C5N fits telecom baseband designs because of its 90,960 logic elements and 384 embedded 18x18 multipliers, which deliver the parallel multiply-accumulate throughput needed for channelization, FEC decoding, and baseband demodulation. The 4.52 Mbit of TriMatrix block RAM buffers symbol-rate data across multiple antenna streams while the 534 user I/O mates to external DDR/QDR memories and high-speed ADCs/DACs. Designers benefit from Quartus II's pre-verified DSP Builder IP cores for FFTs, Viterbi, and Turbo decoders that target Stratix II silicon.

おすすめ

🖥️

ASIC Prototyping and Emulation

With 90,960 logic elements and 4.52 Mbit of embedded memory, the EP2S90F780C5N acts as a multi-million-gate ASIC prototyping vehicle, partitioning large SoC designs across multiple FPGAs via TDM or HTILE-style logic-sharing interfaces. Its 780-ball FBGA exposes 534 user I/O, which supports enough off-chip bandwidth to maintain real-time verification of CPU cores, peripherals, and memory subsystems. Quartus II's TimeQuest timing analyzer and incremental compile flow let design teams iterate the prototype quickly, while the Stratix II ALM preserves high logic utilization compared to 4-LUT families.

おすすめ

EP2S130F780C5N · Intel EP2S180F1508C5N · Altera

🎥

High-Speed Image and Video Processing

The EP2S90F780C5N supports real-time HD video pipelines because its 534 user I/O and TriMatrix memory deliver the bandwidth needed for multi-channel Camera Link, LVDS, or HDMI ingest, while the 384 DSP blocks accelerate 2D convolution, Sobel edge detection, and motion-estimation kernels at full frame rate. Designers use parallel pixel pipelines across the ALM fabric, distributing frame buffers across M4K and M-RAM blocks to avoid off-chip memory bottlenecks. Quartus II's Video and Image Processing (VIP) suite provides ready-made IP for color space conversion, scaling, and deinterlacing that maps directly to the ALM and DSP resources.

おすすめ

EP2S90F780C4N · Intel EP2S90F1508C5N · Intel

✈️

Military and Aerospace Signal Processing

The EP2S90F780C5N's commercial 0-85C range can be extended via the EP2S90F780I5N industrial-grade counterpart for ruggedized signal-processing applications in radar, electronic warfare, and avionics where MIL-STD-810 environmental qualification is required. The 90K LE capacity and 384 DSP blocks enable pulse-compression, beamforming, and synthetic-aperture-radar (SAR) back-projection at real-time rates, while the lead-free FBGA withstands typical aerospace reflow profiles. Designers use the Stratix II hardened PCI Express and SERDES blocks to feed digitized antenna arrays back to mission processors.

おすすめ

EP2S90F780I5N (Industrial-temperature variant for rugged deployments) EP2S130F1020I4N · Intel

🏭

Industrial Control and Test Instrumentation

The EP2S90F780C5N suits industrial test and measurement platforms because its parallel logic and high I/O count allow simultaneous control of multi-axis motor drivers, simultaneous sampling of ADC channels, and real-time computation of control loops in PLLs and DSP blocks. The 4.52 Mbit of embedded RAM holds real-time waveform captures and PID coefficients without external memory, while the 780-BGA provides sufficient I/O for parallel bus interfaces to legacy industrial peripherals. Quartus II's Nios II soft-core lets designers integrate a processor for supervisory control on the same fabric.

おすすめ

EP2S60F484C5N · Intel EP2S30F484C5N · Intel

📡

Software-Defined Radio (SDR) Platforms

The EP2S90F780C5N is well-matched to wideband SDR front-ends because its 384 18x18 multipliers and TriMatrix block RAM implement multi-rate FIR filtering, digital down/up-conversion, and channelizer polyphase filterbanks in real time at sample rates up to hundreds of MSPS. The 534 user I/O accommodates parallel LVDS ADC/DAC interfaces, while the dedicated PLLs provide multiple synchronized sample clocks for MIMO architectures. Designers can pair the FPGA with RF tuners and use Quartus II DSP Builder to generate fixed- or floating-point datapaths that exploit the Stratix II DSP block architecture efficiently.

おすすめ

EP2S130F780C5N · Intel EP2S90F1020C5N · Intel

おすすめ製品の概要

EP2S90F780C4N Intel 使用用途: Telecommunications Baseband Processing, High-Speed Image and Video Processing EP2S130F780C5N Intel 使用用途: Telecommunications Baseband Processing, ASIC Prototyping and Emulation, Software-Defined Radio (SDR) Platforms EP2S180F1508C5N Altera 使用用途: ASIC Prototyping and Emulation EP2S90F1508C5N Intel 使用用途: High-Speed Image and Video Processing EP2S90F780I5N Industrial-temperature variant for rugged deployments 使用用途: Military and Aerospace Signal Processing EP2S130F1020I4N Intel 使用用途: Military and Aerospace Signal Processing EP2S60F484C5N Intel 使用用途: Industrial Control and Test Instrumentation EP2S30F484C5N Intel 使用用途: Industrial Control and Test Instrumentation EP2S90F1020C5N Intel 使用用途: Software-Defined Radio (SDR) Platforms

What is the EP2S90F780C5N and what family does it belong to?

The EP2S90F780C5N is a high-density FPGA from Intel's (formerly Altera's) Stratix II family, built on a 90 nm CMOS process and containing 90,960 logic elements. According to the Stratix II device handbook, it integrates 4,520,488 bits of embedded memory and up to 534 user I/O, making it suitable for DSP, telecom, and high-throughput parallel processing. The 'N' suffix denotes a lead-free, RoHS-compliant package finish.

What package does the EP2S90F780C5N use and what are its dimensions?

The EP2S90F780C5N is supplied in a 780-ball FineLine BGA (FBGA) package measuring 29 x 29 mm with a 1.0 mm ball pitch, as recorded in the Stratix II device handbook. The 'F780' ordering code explicitly maps to the 780-pin FBGA variant. This large BGA requires multilayer PCB construction with microvia or via-in-pad technology for reliable assembly at 1 mm pitch.

What is the core voltage and operating temperature of the EP2S90F780C5N?

The EP2S90F780C5N operates from a 1.2 V core supply with selectable I/O standards (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL), and its commercial-grade junction temperature range is 0C to 85C TJ. Industrial (-40C to 100C TJ) and military variants use different ordering codes such as the EP2S90F780I5N for industrial applications.

Where to buy the EP2S90F780C5N online and what is the current price?

As of 2026-09-09, EP2S90F780C5N stock is scarce because the part is flagged Obsolete in the GlobalSpec distributor database. Verified suppliers include Xecor, Microchip-Price, IC-Components, and semiconductor-electronics.com (per Octopart's listing of 23 distributors). Unit pricing in the open market ranges roughly $250-$320 at qty 1-10; XAIPART tier-1 reference pricing is $285 each.

What is the lead time for the EP2S90F780C5N?

Lead time for the EP2S90F780C5N is unpredictable because it is marked Obsolete; franchised Intel/Altera distributors no longer carry factory-fresh inventory. Brokers and independent distributors (Xecor, IC-Components) typically quote 4-12 weeks for new-old-stock (NOS) or refurbished units, with prices volatile. Designers should qualify a Stratix IV or Cyclone V drop-in alternative and avoid single-source reliance on this EOL part.

Is the EP2S90F780C5N in stock anywhere?

Stock availability is limited and intermittent as of 2026-09-09. Independent distributors and obsolete-component brokers (Xecor, IC-Components, Microchip-Price) periodically list small quantities, often as factory-new surplus. For volume production, treat the EP2S90F780C5N as effectively unavailable from franchised sources - always validate the supplier's chain-of-custody documentation to mitigate counterfeit risk.

EP2S90F780C5N vs EP2S90F780C4N - which should I choose?

Both parts share the same 780-ball FBGA package, 90,960 logic elements, and 4.52 Mbit memory, differing only in speed grade. The 'C5' speed grade is faster (higher Fmax) than 'C4', so EP2S90F780C5N is preferred when timing closure is critical; EP2S90F780C4N is acceptable when margin is comfortable and cost or availability favors it. Both are obsolete; choose C5 if available, then C4, then migrate to a Stratix IV equivalent.

EP2S90F780C5N vs EP2S130F780C5N - which is better for high-density designs?

The EP2S130F780C5N contains 132,540 logic elements versus the EP2S90F780C5N's 90,960, sharing the same 780-ball FBGA footprint and Stratix II family. For designs that fit within 90K LE, the EP2S90 is the lower-cost option. For designs needing 100K-130K LE or larger memory, the EP2S130F780C5N is the same-package upgrade path. Both share pinout compatibility, simplifying migration.

When should I choose the EP2S90F780C5N over a Cyclone IV or Cyclone V device?

Choose the EP2S90F780C5N only when you have legacy code targeting the Stratix II ALM architecture or when long-term production designs require exact second-source continuity of an obsolete part. For new designs, Intel's Cyclone V or MAX 10 offer lower cost, lower power, and active lifecycle support at the expense of logic density - the Cyclone V 5CGXFC7C7F23C8N tops out at 149K LE but in a smaller, cheaper package.

What is the best drop-in replacement for the obsolete EP2S90F780C5N?

Within the Stratix II family, the EP2S90F780C4N is the closest drop-in alternative: identical 780-ball FBGA package, identical 90,960 logic elements and 4.52 Mbit memory, but a slower C4 speed grade (par1 PARAM_MATCH 90). The EP2S130F780C5N offers the same footprint with higher logic density (132K LE) for design growth, while the EP2S90F780I5N is the industrial-temperature variant. For migration to active-lifecycle silicon, the Stratix IV EP4SGX230KF40C2N is functionally similar but uses a different package.

Can the EP2S90F780I5N replace the EP2S90F780C5N?

The EP2S90F780I5N can replace the EP2S90F780C5N on the same 780-ball FBGA footprint with identical 90,960 logic elements and 4.52 Mbit memory. The difference is operating temperature: 'C5' is commercial 0C-85C, 'I5' is industrial -40C-100C, with the same speed grade 5. The drop-in replacement is acceptable for designs needing industrial temperature headroom at the cost of slightly higher unit pricing.

Where to download the EP2S90F780C5N datasheet PDF?

The official Stratix II device handbook is hosted at intel.com as the authoritative datasheet for the EP2S90F780C5N. Third-party mirrors (datasheets.com, Octopart, GlobalSpec) also host the PDF. XAIPART links to the manufacturer-hosted PDF to ensure the latest revision; engineers should also reference AN 306 (Stratix II transceiver guidelines) and AN 341 (external memory interface) for application-level design.

Where can I find the EP2S90F780C5N pinout (ball map)?

The 780-ball FBGA pinout for the EP2S90F780C5N is published in the Stratix II Device Handbook, Chapter 9 'Package Information'. Intel provides per-package ball maps for every I/O bank and dedicated pin (PLL, JTAG, configuration, clock). Use Quartus II Pin Planner to load the .qsf pin assignment file directly - this is the recommended workflow because manual pin mapping of a 780-ball BGA is error-prone.

What are the key specifications of the EP2S90F780C5N that engineers should know?

The EP2S90F780C5N key specs are: 90,960 logic elements (45,960 ALMs), 4,520,488 embedded memory bits across TriMatrix blocks, up to 534 user I/O, 384 embedded 18x18 multipliers for DSP, 1.2 V core supply, 90 nm CMOS process, 609.76 MHz internal Fmax, 780-ball FBGA at 29 x 29 mm, commercial 0C-85C temperature, lead-free finish. Lifecycle: Obsolete per GlobalSpec distributor records (2026-09-09).

エンジニアリング参考データ: EP2S90F780C5N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP2S90F780C5N when you have a legacy Stratix II design that requires exact bit-for-bit second-source continuity and you cannot accept the risk of migrating to a different FPGA family. For new designs, prefer the EP2S90F780C4N if timing closure is comfortable and you need a marginally more available part; choose the EP2S130F780C5N on the identical 780-BGA when your design grows past 90K LE, since it shares the same pinout and reflow profile. For active-lifecycle silicon, migrate to the Stratix IV EP4SGX230 family (different package) or Cyclone V 5CGXFC7 - these are not drop-in but offer factory support and lower cost. Always validate obsolete-part supply chain via franchised distributors before committing to production.

代替品との比較

パラメータ	この製品	EP2S90F780C5	EP2S90F780C4N	EP2S90F780C4	EP2S130F780C5N	EP2S130F780C5
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	780-ball FBGA, 29x29 mm, 1.0 mm pitch	780-ball FBGA - same	780-ball FBGA - same	780-ball FBGA - same	780-ball FBGA - same	780-ball FBGA - same
Family	Stratix II	Stratix II	Stratix II	Stratix II	Stratix II	Stratix II
Logic Elements	90,960	90,960 - same	90,960 - same	90,960 - same	132,540 (+46%)	132,540 (+46%)
Embedded Memory	4,520,488 bits	4,520,488 bits - same	4,520,488 bits - same	4,520,488 bits - same	6,747,840 bits (+49%)	6,747,840 bits (+49%)
Speed Grade	C5	C5 - same	C4 (slower ~10-15%)	C4 (slower ~10-15%)	C5 - same	C5 - same
Embedded 18x18 Multipliers	384	384 - same	384 - same	384 - same	504 (+31%)	504 (+31%)
Operating Temperature	0C to 85C (commercial)	0C to 85C - same	0C to 85C - same	0C to 85C - same	0C to 85C - same	0C to 85C - same
Lead-Free (N suffix)	Yes	No (SnPb finish)	Yes	No (SnPb finish)	Yes	No (SnPb finish)

主な差別化要因

Higher-density drop-in on same 780-BGA footprint （vs EP2S90F780C4N)
Faster speed grade over C4 equivalent （vs EP2S90F780C4N)
Lead-free finish for RoHS/automotive compliance （vs EP2S90F780C5 (no 'N' suffix))

設計ノート

The 780-ball FBGA at 1.0 mm pitch has a relatively high junction-to-ambient thermal resistance; for sustained high-utilization designs (above ~70% logic utilization at 200+ MHz), design 4+ thermal vias under the central BGA ball grid and at least 8 thermal vias directly beneath the die flag. Stratix II power can exceed 10 W under full DSP load - consider forced airflow or a heatsink attached with thermal interface material. Junction temperature must remain below 85C for the commercial-grade EP2S90F780C5N; use the EP2S90F780I5N for industrial deployments.

A 1.0 mm pitch FBGA requires a multilayer PCB stack-up with HDI microvias or via-in-pad construction for reliable assembly. Recommended stack-up: 8+ layers with 0.5 oz copper outer / 1 oz copper inner, FR-4 high-Tg (Tg >=170C) dielectric, and ENIG surface finish. Use a 4-6 mil BGA pad diameter with solder mask-defined (SMD) pads to reduce bridging risk. Reference Intel AN 224 'Stratix II Board Design Guidelines' for detailed escape routing recommendations.

Stratix II PLLs require clean, isolated power (VCCA_PLL) with a pi-filter (ferrite bead + decoupling caps) and a dedicated ground island connected to the main ground plane at a single point. Place differential clock inputs (CLK[0..15]) within the dedicated clock input region with matched-length, 50 ohm impedance-controlled traces; keep these traces far from switching I/O to avoid coupling. Dedicated configuration pins (nCONFIG, nSTATUS, CONF_DONE) must be pulled to their idle states per the configuration scheme chosen in Quartus II Device & Pin Options.

Estimated: this part is marked Obsolete as of 2026-09-09 per the GlobalSpec distributor database - do not commit new high-volume production designs to it. Verify all Stratix II configurations, JTAG IDs, and pinout files in Quartus II v13.1 (the last officially supported IDE for Stratix II); do not use newer Quartus versions, which drop legacy device support. When migrating to Stratix IV or Cyclone V, be aware that ALM-to-LAB mapping and DSP block architectures differ - recompile all IP cores and re-validate timing closure.

コンプライアンス情報

RoHS

Compliant

REACH

Unknown

AEC-Q100

Not Applicable

鉛フリー

Yes

ハロゲンフリー

Unknown

紛争鉱物

Unknown

RoHS compliance per datasheets.com listing (lead-free 'N' suffix). REACH, halogen-free, and conflict-minerals status not stated in the verified web data; AEC-Q100 not applicable for FPGAs.

データ検証日: 2026-09-09 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Manufacturer Datasheet, Manufacturer Product Page, Octopart, Distributor, Distributor