EP2SGX90FE1152C3 - 90K LE Stratix II GX FPGA, 1152-BGA | Intel
部品番号: EP2SGX90FE1152C3 ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 25 | $1650 | $41,250.00 |
| 50 | $1580 | $79,000.00 |
| 100 | $1495 | $149,500.00 |
EP2SGX90FE1152C3 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs) connected by a programmable interconnect matrix, with hardened I/O, memory, and increasingly serial transceiver and DSP resources. Within the broader taxonomy, the EP2SGX90FE1152C3 is an FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit (IC) -> semiconductor. Stratix II GX parts belong to Intel's high-end transceiver-equipped FPGA family, positioned above Cyclone and Arria in performance and below Stratix IV/V in the product lineage.
Key features include 4,548 LABs/CLBs, 558 user I/Os, 192 (18x18) multiplier blocks supporting DSP functions, and dynamic phase alignment (DPA) on the multi-gigabit transceivers. The 1152-ball FC-FBGA package provides 1 mm or finer ball pitch and supports industrial-grade reflow profiles. Configuration is supported via passive serial (PS), passive parallel synchronous/asynchronous (PPS/PPA), fast passive parallel (FPP), and JTAG modes through the dedicated configuration pins.
Typical applications include 10 Gbps optical transport, baseband processing for LTE/UMTS, video bridging and scaling, high-speed serial backplanes, and PCI Express Gen1/Gen2 endpoint designs. The combination of high logic density, abundant block RAM, and 6.375 Gbps transceivers makes this device suitable for protocol bridging ASIC replacement and signal-intelligence DSP pipelines.
When designing with this part, pay close attention to transceiver reference clock jitter (typically < 1 ps RMS for 6.375 Gbps operation), PCB stack-up for 1 mm-pitch BGA breakout, and decoupling strategy (decoupling guidelines are documented in the Stratix II GX device handbook). Power estimation should use the Early Power Estimator (EPE) before RTL freeze to size rails and thermal solution accurately. Ensure JTAG chain integrity and proper MSEL pin settings for the chosen configuration scheme.
This page synthesizes distributor pricing (as of 2026-09-09), drop-in same-package alternatives, comparison data, and practical design notes for the EP2SGX90FE1152C3 in a single reference. The same-family Intel/Altera Stratix II GX 1152-BGA variants (different speed, temperature, and core-voltage suffixes) are listed as drop-in alternatives where pinout and ball map are identical to the C3-grade device, allowing PCB reuse across the variant matrix.
ドロップイン代替品: EP2SGX90FE1152C3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2SGX90FE1152C3 （同一形状・フットプリント） — 相違点: Package, Total RAM Bits, Core Voltage, Operating Temperature, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP2SGX90EF1152C3
✅ ドロップイン✓ 在庫あり
$1180 / 個
データシートを見る →EP2SGX90EF1152C3N
✅ ドロップイン✓ 在庫あり
$1280 / 個
データシートを見る →EP2SGX90EF1152C3ES
✅ ドロップイン✓ 在庫あり
$2050 / 個
データシートを見る →EP2SGX90F1152C3N
✅ ドロップイン✓ 在庫あり
$175 / 個
データシートを見る →EP2SGX90EF1152C4
✅ ドロップイン✓ 在庫あり
$890 / 個
データシートを見る →EP2SGX90EF1152C5
✅ ドロップイン✓ 在庫あり
$225 / 個
データシートを見る →EP2SGX90EF1152I3
✅ ドロップイン✓ 在庫あり
$1480 / 個
データシートを見る →EP2SGX90EF1152I3N
✅ ドロップイン✓ 在庫あり
$1320 / 個
データシートを見る →EP2SGX90FE1152C3 最大定格＆電気的特性
| Series | Stratix II GX |
| Family Name | Stratix II GX |
| Logic Elements / Cells | 90,960 |
| Total RAM Bits | 4,520,448 |
| Number of LABs / CLBs | 4,548 |
| Number of Logic Elements / Cells | 90,960 |
| Number of I/O | 558 |
| Voltage - Supply | 1.2 V core |
| 動作温度 | 0C to +85C (commercial, C3 suffix) |
| 実装タイプ | Surface Mount (BGA) |
| パッケージ / ケース | 1152-BBGA / FC-FBGA |
| Process Technology | 90 nm CMOS |
| Transceiver Data Rate (max) | 6.375 Gbps |
| Number of Transceiver Channels | 12 |
| DSP Blocks (18x18 multipliers) | 192 |
| Configuration Support | PS, PPS, PPA, FPP, JTAG |
EP2SGX90FE1152C3 1152-bbga / fc-fbga ピン配置ガイド
EP2SGX90FE1152C3 (1152-bbga / fc-fbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP2SGX90FE1152C3.
詳細は データシート をご参照ください。
主な用途
EP2SGX90FE1152C3 の用途: 6 件s: 10 Gbps Optical Transport and Backplane Interface, Wireless Baseband Processing (LTE / UMTS), Video Bridging, Scaling, and Format Conversion, PCI Express Endpoint / Root Complex, High-Speed Serial Backplane Aggregation, ASIC Replacement / NPI Prototyping.
10 Gbps Optical Transport and Backplane Interface
The EP2SGX90FE1152C3 supports 12 multi-gigabit transceiver channels up to 6.375 Gbps, which is well matched to 10 GbE LX4, XAUI, and 4x Fibre Channel ports when two transceivers are aggregated per 10 Gbps link. Its 90,960 LEs and 192 18x18 multipliers allow the device to host the MAC, PCS, and forward-error-correction logic alongside small packet-processing datapaths. Compared with a discrete PHY plus ASIC, integrating these functions in one FPGA reduces BOM cost and simplifies timing closure. Use Stratix II GX device-handbook reference designs for XAUI to reduce bring-up time. Industrial-grade variants cover the temperature range needed for optical line cards in central offices.
おすすめ
Wireless Baseband Processing (LTE / UMTS)
The 192 18x18 multipliers and 4,520,448 bits of embedded TriMatrix memory make the EP2SGX90FE1152C3 a viable host for LTE downlink/uplink baseband PHY layers, including channel estimation, FFT/iFFT, and turbo decoding. The 12 transceivers connect to radio front ends and backhaul links at 6.375 Gbps, supporting CPRI/OBSAI fronthaul aggregation. The 1152-ball BGA package supports industrial-grade airflow and cold-plate cooling, which are common in base-station shelves. For higher-density next-generation radios, the EP2SGX130/230 family or the Stratix IV family provide a migration path but require PCB redesign.
おすすめ
Video Bridging, Scaling, and Format Conversion
The 558 user I/Os of the EP2SGX90FE1152C3 are sufficient to host multiple parallel video interfaces (RGB/YCbCr, BT.1120, DisplayPort 1.1a via LVDS), while the 4,520,448 bits of embedded memory provide line buffers for scaling and deinterlacing. The 192 DSP blocks support 2D adaptive filtering and noise reduction. The 6.375 Gbps transceivers accept SDI and DisplayPort 1.1a inputs. The Altera Video and Image Processing (VIP) megafunction suite accelerates time-to-market for video pipelines. Industrial-temperature variants are suitable for broadcast and digital-signage installations.
おすすめ
PCI Express Endpoint / Root Complex
The EP2SGX90FE1152C3 supports PCIe Gen1 (2.5 Gbps) and PCIe Gen2 (5 Gbps) endpoints via the integrated transceivers, with the Altera PCIe hard IP providing the PHY-MAC and the transaction layer. The 90,960 LEs and 4,520,448 bits of memory are sufficient to host a DMA engine, device drivers in soft logic, and optional protocol offload for NVMe, Ethernet, or custom protocols. The 1152-ball BGA supports a PCIe edge-finger layout and standard 1U add-in-card form factors. For Gen3 (8 Gbps) operation, migrate to Stratix V or Cyclone 10 GX families.
おすすめ
High-Speed Serial Backplane Aggregation
The 12 transceivers at 6.375 Gbps aggregate up to 12 lanes of Serial RapidIO, Aurora, or proprietary serial backplane traffic. The 558 I/Os provide ample GPIO for board control, I2C, SPI, and parallel status buses. The 4,548 LABs and 192 DSP blocks are sufficient to host error-correction, encryption, and protocol-translation logic. The 1152-ball BGA supports dense board layouts with the high-pin-count that backplane cards require. Industrial variants are appropriate for the rugged temperature range of telecom backplane equipment.
おすすめ
ASIC Replacement / NPI Prototyping
For low-volume new-product introduction (NPI), the EP2SGX90FE1152C3 lets design teams validate an architecture in reconfigurable logic before committing to an ASIC mask set, saving NRE and reducing risk. The 90,960 LEs, 4,520,448 bits of memory, and 192 DSP blocks cover a wide range of signal-processing and protocol-handling applications. The 1152-ball BGA is a standard high-density package that simplifies PCB layout. The same 1152-ball BGA footprint is shared across the Stratix II GX EP2SGX90 family, allowing PCB reuse across speed-grade and temperature-grade variants for different product SKUs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2SGX90FE1152C3 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2SGX90EF1152C3 | EP2SGX90EF1152C3N | EP2SGX90EF1152C3ES | EP2SGX90F1152C3N | EP2SGX90EF1152C4 | EP2SGX90EF1152C5 | EP2SGX90EF1152I3 | EP2SGX90EF1152I3N |
|---|---|---|---|---|---|---|---|---|---|
| Package | 1152-BBGA (FC-FBGA) | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same | 1152-BBGA (FC-FBGA) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | C3 (mid commercial) | C3 | C3 | C3 | C3 | C4 | C5 | I3 | I3 |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Temperature Grade | Commercial (0C to +85C) | Commercial | Commercial | Commercial (ES) | Commercial | Commercial | Commercial | Industrial | Industrial |
| Lead-Free / RoHS | Per lot (markings vary) | Per lot | Yes (N suffix) | Per lot | Yes (N suffix) | Per lot | Per lot | Per lot | Yes (N suffix) |
| Transceiver Rate (max) | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy (ES) | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
主な差別化要因
- Same-package drop-in compatibility across the Stratix II GX EP2SGX90 1152-BGA matrix （vs EP2SGX90EF1152C3)
- Industrial temperature variants available on the same footprint （vs EP2SGX90EF1152I3N)
- Lead-free option (N suffix) on the same 1152-ball footprint （vs EP2SGX90EF1152C3N)
設計ノート
Estimated: At full transceiver activity (12 channels at 6.375 Gbps PRBS-31) and 70% logic utilization, the EP2SGX90FE1152C3 can dissipate 18-25 W. Use the Altera Early Power Estimator (EPE) with your specific utilization before RTL freeze to size the 1.2 V core rail, the 2.5 V/3.3 V aux rails, and the transceiver PLL supply. For typical lab designs, allocate at least a 0.1 uF X7R decoupling cap per power pin and bulk ceramics on the PCB side of the BGA fanout. The Stratix II GX device handbook contains a recommended decoupling network for each power rail.
The 1152-ball FC-FBGA package requires a 1.0 mm (typical) ball pitch PCB breakout. Use a 1-2-1 or 1-2-2-2 microvia stack-up to fan out inner rows without dog-bone fanouts. Match the length of the transceiver TX/RX differential pairs within 5 mil tolerance, and use 100-ohm differential impedance. For the 6.375 Gbps channels, follow the Altera Stratix II GX board design guidelines for via-stub minimization, AC-coupling capacitor placement, and reference-plane continuity under the high-speed serial lanes. BGA-1152 layout is non-trivial - engage a layout service with high-speed serial experience if you lack in-house expertise.
Do not mix up the MSEL[2:0] strapping pins for configuration mode selection - the wrong strap will fail to configure the device silently. Do not leave the JTAG TCK pin floating; pull to a defined state with a 1-10 kohm resistor. Do not share the transceiver reference-clock differential pair with another device's clock output, as jitter coupling will degrade eye-margins. The configuration controller reset (nCONFIG, nSTATUS) must be debounced correctly, otherwise the device may not exit POR reliably on noisy power rails. Refer to the configuration handbook for the recommended RC values on nCONFIG.
At 22 W of power dissipation, the EP2SGX90FE1152C3 in 1152-ball FC-FBGA typically needs forced airflow (1-2 m/s) or a heat-spreader to keep the junction below 100C. Without airflow, the package can exceed commercial-grade temperature limits within 60 seconds of full activity. Use a thermal pad and a heat-spreader on the package top for convection-cooled applications; for industrial-temperature variants, the spreader becomes essential. Validate with a thermal-coupon measurement before finalizing the mechanical design.
Estimated: For 6.375 Gbps serial channels, a 3 dB insertion-loss budget at 3.1875 GHz (Nyquist) is typical. Use Megtron-6 or similar low-loss PCB material for backplane routes longer than 6 inches. AC-coupling capacitors on the TX serial lanes must be 0402 size for the lowest parasitic inductance. Receiver channels benefit from the Altera DPA (Dynamic Phase Alignment) block to relax channel ISI. Always run post-layout IBIS-AMI simulation to validate eye-margins before committing to PCB fabrication.
コンプライアンス情報
RoHS, REACH, lead-free, and halogen-free status for the EP2SGX90FE1152C3 was not stated in the verified web data. Lot-level markings on the BGA package must be inspected for actual lead-free and halogen-free status. AEC-Q100 is not applicable because this is an FPGA rather than an automotive-grade automotive IC (automotive-grade FPGA programs would typically use automotive-qualified Cyclone or Stratix variants, not legacy Stratix II GX).
