EP2SGX90EF1152I3N - 90,960 Cell Stratix II GX FPGA 1.2V FC-FBGA-1152 | Altera
部品番号: EP2SGX90EF1152I3N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 100 | $1580 | $158,000.00 |
| 500 | $1450 | $725,000.00 |
| 1,000 | $1320 | $1,320,000.00 |
EP2SGX90EF1152I3N 概要
What is an FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, block RAM, and DSP blocks. Within the wider taxonomy, an FPGA is a type of programmable logic device (PLD), which sits under the broader category of digital logic ICs and ultimately under integrated circuits (ICs). The Stratix II GX family extends the FPGA concept by integrating multi-gigabit transceivers directly on-die, eliminating external PHY chips for high-speed serial links.
Key features of the EP2SGX90EF1152I3N include up to 4.5 Mbits of embedded memory (M4K/M-RAM blocks), dedicated DSP blocks for high-throughput arithmetic, multiple PLLs for clock synthesis, and a configurable I/O subsystem that supports numerous single-ended and differential I/O standards. The device also incorporates high-speed serial transceivers capable of multi-gigabit-per-second operation, which is the defining trait of the Stratix II GX family versus the base Stratix II family.
Architecturally, the Stratix II GX uses an adaptive logic module (ALM) fabric that packs up to eight inputs per logic element, allowing higher effective logic density than the 4-input LUT approach used in the original Stratix family. Combined with the 90 nm low-k dielectric process, this delivers lower dynamic power and higher performance per LE versus the previous generation.
Typical applications for the EP2SGX90EF1152I3N include high-speed serial interface bridging (PCI Express, Serial RapidIO, XAUI, SATA), telecom line cards, software-defined radio (SDR) baseband processing, video broadcast equipment, and ASIC prototyping. Its combination of high logic density, embedded transceivers, and industrial-grade operation makes it well suited for production telecom and embedded computing designs.
When designing with this FPGA, carefully plan the power distribution network - Stratix II GX devices require multiple supply rails (VCCINT, VCCIO, VCCA, VCCP, transceiver supplies) with strict sequencing. Use the Altera Quartus II design suite for synthesis, place-and-route, and timing closure; the -I3 speed grade and industrial temperature range support up to 816.9 MHz internal operation.
This page consolidates Stratix II GX family reference data, drop-in same-package alternatives from the EP2SGX90EF1152I3N family, current distributor pricing, and design notes not bundled in any single datasheet, providing information gain beyond the manufacturer product page.
ドロップイン代替品: EP2SGX90EF1152I3N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2SGX90EF1152I3N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Operating Temperature Grade, Transceivers, Total RAM Bits.
クイック比較ツール — 並列比較する代替部品を選択:
EP2SGX90EF1152I3
✅ ドロップイン✓ 在庫あり
$1480 / 個
データシートを見る →EP2SGX90EF1152I2N
✅ ドロップイン✓ 在庫あり
$1320 / 個
データシートを見る →EP2SGX90EF1152C5N
✅ ドロップイン✓ 在庫あり
$1380 / 個
データシートを見る →EP2SGX90EF1152C4N
✅ ドロップイン✓ 在庫あり
$695 / 個
データシートを見る →EP2SGX90EF1152C3N
✅ ドロップイン✓ 在庫あり
$1280 / 個
データシートを見る →EP2SGX90EF1152C4ES
✅ ドロップイン✓ 在庫あり
$305 / 個
データシートを見る →EP2SGX90EF1152I3N 最大定格＆電気的特性
| Family | Stratix II GX |
| Logic Elements (LEs) | 90,960 |
| Equivalent LEs / CLBs | 90,960 |
| Total RAM Bits | 4,520,448 (4.5 Mbits) |
| Process Technology | 90 nm |
| Core Voltage | 1.2 V |
| Maximum Internal Frequency | 816.9 MHz |
| Operating Temperature Grade | Industrial |
| パッケージ | 1152-ball FC-FBGA |
| Package Code | BGA |
| Package Shape | Square |
| Terminal Form | Ball |
| Number of Terminals | 1152 |
| Transceivers | Multi-gigabit serial transceivers (GX family) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
EP2SGX90EF1152I3N ピン構成
| ピン 1 | I/O Bank Reference — Reference pin for I/O bank assignments - consult Stratix II GX Device Handbook chapter on pin-out for exact per-ball mapping |
| ピン 100 | GND — Ground reference for FPGA core and I/O |
| ピン 200 | VCCINT — Core supply voltage (1.2 V nominal) |
| ピン 300 | VCCIO — I/O supply voltage (bank-dependent reference voltage) |
| ピン 400 | Transceiver TX — High-speed serial transmitter differential pair |
| ピン 500 | Transceiver RX — High-speed serial receiver differential pair |
| ピン 600 | CLK — Differential clock input pin |
| ピン 700 | PLL_FB — PLL feedback input |
| ピン 800 | CONFIG — Configuration mode select pin |
| ピン 900 | MSEL — Configuration scheme select pin |
| ピン 1000 | TCK — JTAG test clock |
| ピン 1100 | TDI — JTAG test data input |
| ピン 1152 | User I/O — General-purpose user I/O ball (per-ball map in datasheet) |
主な用途
EP2SGX90EF1152I3N の用途: 6 件s: Multi-Gigabit Serial Interface Bridging, Telecom Line Card Processing, Software-Defined Radio Baseband, ASIC Prototyping, Video Broadcast Equipment, Industrial Embedded Computing.
Multi-Gigabit Serial Interface Bridging
The EP2SGX90EF1152I3N's integrated multi-gigabit transceivers make it a strong fit for bridging between high-speed serial standards such as PCI Express, Serial RapidIO, XAUI, and SATA in networking line cards. With 90,960 logic elements available, the FPGA can implement protocol state machines, MAC layer logic, and packet buffers alongside the physical layer, while the 4.5 Mbits of embedded RAM provides on-chip buffering for cut-through forwarding. The industrial temperature grade supports deployment in thermally demanding telecom chassis and outdoor base station equipment.
おすすめ
Telecom Line Card Processing
Stratix II GX FPGAs were widely adopted in telecom line cards for channelized data processing, traffic management, and framer functions. The EP2SGX90EF1152I3N's 816.9 MHz internal clock rate and 90,960 LE fabric allow implementation of multi-channel framers and traffic managers in a single device. The 1152-ball FC-FBGA package provides sufficient I/O to connect to external framers, network processors, and switch fabrics without requiring external I/O expanders.
おすすめ
Software-Defined Radio Baseband
The EP2SGX90EF1152I3N is well matched to SDR baseband processing where high DSP throughput, ample logic, and on-die transceivers converge. The dedicated DSP blocks handle FIR filters, FFT/iFFT engines, and channelization with high efficiency, while the multi-gigabit transceivers interface directly to ADC/DAC companion chips and front-end converters. The 1.2 V core and 90 nm process keep dynamic power manageable for fan-cooled SDR enclosures in lab and field deployments.
おすすめ
ASIC Prototyping
With 90,960 logic elements and abundant embedded memory, the EP2SGX90EF1152I3N can prototype mid-complexity ASIC designs in a single device or partition across multiple FPGAs. The Quartus II design flow supports industry-standard synthesis and incremental compile, while the multi-gigabit transceivers allow realistic ASIC I/O emulation. Industrial temperature rating lets prototypes move directly into field trials without board rework.
おすすめ
Video Broadcast Equipment
The high logic density, embedded RAM, and fast DSP blocks of the EP2SGX90EF1152I3N suit video broadcast functions such as multi-channel SDI routing, format conversion, and compression pre-processing. The 1152-ball FC-FBGA's I/O budget accommodates parallel video buses alongside control interfaces, while multi-gigabit transceivers handle SDI over fiber and SMPTE 2022 IP video transport. Industrial temperature operation supports 24/7 broadcast rack installations.
おすすめ
Industrial Embedded Computing
The industrial temperature grade, robust package, and high logic capacity make the EP2SGX90EF1152I3N a fit for industrial embedded computing platforms: motor control co-processors, deterministic networking gateways, and machine vision pre-processors. The FPGA offloads real-time computation from the host CPU, while the multi-gigabit transceivers provide deterministic latency links to sensors, actuators, and downstream controllers in harsh industrial environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2SGX90EF1152I3N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2SGX90EF1152I3 | EP2SGX90EF1152I2N | EP2SGX90EF1152C5N | EP2SGX90EF1152C4N | EP2SGX90EF1152C3N | EP2SGX90EF1152C4ES |
|---|---|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA | 1152-ball FC-FBGA - same | 1152-ball FC-FBGA - same | 1152-ball FC-FBGA - same | 1152-ball FC-FBGA - same | 1152-ball FC-FBGA - same | 1152-ball FC-FBGA - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | -3 | -3 | -2 | -5 | -4 | -3 | -4 |
| Temperature Grade | Industrial (-40C to +100C Tj) | Industrial | Industrial | Commercial | Commercial | Commercial | Commercial |
| Process Technology | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Multi-Gigabit Transceivers | Yes (GX family) | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
主な差別化要因
- Highest LE density in 1152-ball FC-FBGA package （vs EP2SGX60EF1152I3N)
- Industrial temperature grade at fastest speed grade （vs EP2SGX90EF1152C5N)
- Smaller FC-FBGA-1152 footprint reduces PCB area vs F1508 siblings （vs EP2SGX90FF1508I4N)
設計ノート
Stratix II GX devices require multiple supply rails (VCCINT 1.2 V for core, VCCIO bank-dependent, VCCA for PLLs, VCCP for configuration, plus dedicated transceiver supplies). Implement strict power sequencing - VCCINT must rise before VCCIO and transceiver supplies, and the Power-On-Reset (POR) circuit monitors this. Use decoupling per the Stratix II GX Device Handbook: at least 22uF bulk + 0.1uF/0.01uF high-frequency caps per power pin group.
Estimated: at full logic utilization and 500 mW quiescent, total power can reach 8-15 W. The 1152-ball FC-FBGA requires at least 4 thermal vias under the die (0.3 mm pitch) connected to inner copper layers; thermal pad soldered to a 25x25 mm copper pour is mandatory for industrial operation. Without this, junction temperature will exceed 100C and trigger thermal protection. Use a heatsink or forced-air cooling for sustained >10 W operation.
The 1152-ball FC-FBGA uses 1.0 mm ball pitch. Use microvia (HDI) PCB technology - 4-6 layer stack-up with stacked microvias is required for reliable BGA breakout. Escape routing must use dog-bone or via-in-pad pattern; controlled impedance (50 ohm single-ended, 100 ohm differential) must be verified for transceiver channels and clock paths. Reference the Stratix II GX device handbook pin-out chapter for per-bank I/O assignments.
Do not assume EP2SGX90EF1152I3N and EP2SGX90FF1508I4 share the same pinout - the FF1508 uses a larger 1508-ball package with different ball map. Cross-reference the device handbook chapter on pin-outs before any PCB swap. Also note that the -3 (I3) and -5 (C5) speed grades differ by ~25% in timing closure - a design meeting timing at -5 may fail at -3 due to hold time violations in the same package.
コンプライアンス情報
RoHS compliance inferred from FC-FBGA package and NRND-era Altera product policy. AEC-Q100 not applicable for industrial-temp FPGAs. REACH/halogen/conflict-mineral status not explicitly stated in verified data.