Intel

EP4CGX110DF31C6N - Cyclone IV GX FPGA, 109K LE, 896-FBGA | Intel

部品番号: EP4CGX110DF31C6N ✓ 生産中

在庫あり 1〜3営業日以内に発送

1.2 V Vdss 896-ball FBGA (F31) Package C6 Speed 5,621,760 bits Memory

開始価格 $175 USD / 個

MOQ: 1 |

価格更新日: 2026-09-09

ボリューム価格

数量	単価	小計
1	$285	$285.00
10	$256	$2,560.00
100	$228	$22,800.00
500	$198	$99,000.00
1,000	$175	$175,000.00

ℹ️ すべての価格はUSDです

データシートを見る (PDF) 代替品を見る

数量

EP4CGX110DF31C6N 概要

The Intel (formerly Altera) EP4CGX110DF31C6N is a Cyclone IV GX field-programmable gate array (FPGA) integrating 109,424 logic elements, 5,621,760 bits of embedded memory, and 475 user I/O pins in a 896-ball FineLine BGA (FBGA) package. Built on a low-power 60 nm process, the device operates from a 1.2 V core supply and supports up to eight integrated 3.125 Gbps transceivers, making it suited for cost-sensitive serial-interface applications. The "C6" speed grade indicates a commercial temperature range of 0C to +85C with a -6 speed bin.

An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit whose logic fabric, routing, and I/O behaviour are defined by a user-supplied configuration bitstream rather than by the silicon vendor. FPGAs sit within the broader taxonomy of programmable logic devices (PLDs) - alongside CPLDs - and are used to implement arbitrary digital logic, memory blocks, arithmetic units, and protocol controllers without custom ASIC NRE. The Cyclone IV GX family specifically targets low-cost, transceiver-equipped designs in the FPGA -> programmable logic -> digital semiconductor hierarchy.

Key differentiating features include 156 embedded 18x18 multipliers for DSP workloads, 4 PLLs for clock synthesis, and a hard PCIe Gen1 controller. The 896-ball FBGA package supports high-density board designs where signal integrity, controlled-impedance routing, and power-integrity decoupling are critical. Cyclone IV GX is the lowest-cost Altera/Intel family with multi-gigabit transceivers, often displacing discrete PHY plus CPLD combinations.

In terms of architecture, the EP4CGX110 uses Logic Array Blocks (LABs) containing 16 logic elements each, M9K memory blocks, and distributed MLAB memory. Configuration is loaded via JTAG, Active Serial (AS), or Passive Parallel (PPS) modes from external flash. The device is supported by Intel Quartus Prime design software across the full Cyclone IV GX tool flow.

Typical applications include industrial machine vision, broadcast video processing, low-cost wireline protocol bridging, and PCI Express endpoint cards. The transceiver channels suit SFP/QSFP cages, CPRI links for small-cell base stations, and LVDS/Sub-LVDS display bridging. With 475 user IOs the part also drives wide parallel buses for legacy interface replacement.

When designing with this device, allocate at least one full PCB layer pair for power delivery and use 0402/0201 decoupling placed as close as possible to every BGA ball. Series-termination resistors on LVDS/Sub-LVDS pairs are recommended within 5 mm of the FPGA pin.

This page synthesizes verified distributor pricing, drop-in Cyclone IV GX alternatives, and practical board-design notes not found in the manufacturer datasheet alone.

ドロップイン代替品: EP4CGX110DF31C6N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP4CGX110DF31C6N （同一形状・フットプリント） — 相違点: Package, Speed Grade, Embedded Memory, Family, RoHS Status.

EP4CE75F29C8N

Intel

Package: 780-FBGA (29x29 mm, F29)

RoHS Status: Compliant

比較対象 EP4CGX110DF31C6N →

EP4CGX110CF23C7N

Altera

Speed Grade: 7

RoHS Status: Compliant (N suffix)

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF27C8N

Intel

Speed Grade: C8 (commercial)

Family: Cyclone IV

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF31C7

Intel

Package: 896-FBGA

Speed Grade: 7

Embedded Memory: 5490 Kbits (M9K blocks)

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF31C7N

Intel

Speed Grade: C7 (commercial)

RoHS Status: Compliant

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF31C8

Intel

Package: 896-FBGA, 31 mm x 31 mm, 1 mm pitch

Embedded Memory: 5,621,760 bits (M9K blocks)

Family: Cyclone IV GX (EP4CGX110)

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF31C8N

Intel

Package: 896-ball FineLine BGA (F31), 31 mm

Speed Grade: 8

RoHS Status: Compliant

比較対象 EP4CGX110DF31C6N →

EP4CGX110DF31I6N

Intel

Package: 896-BGA (FineLine BGA)

RoHS Status: Compliant

比較対象 EP4CGX110DF31C6N →

✅ ドロップイン

📦 896-ball FBGA (F31)

same F31 896-ball package, 149,760 logic elements versus 109,424 (+37 percent logic), pin-to-pin compatible

📋 参考代替品（カタログ未掲載）

EP4CE75F29C8N

✅ ドロップイン

Intel

📦 FBGA-780 (F29)

Cyclone IV E · 75,408 · 4713 · 2,810,880 · 426 · 75,408 · 1.15 V to 1.25 V

✓ 在庫あり

$149.75 / 個

データシートを見る →

EP4CGX110DF31C6N 最大定格＆電気的特性

Family	Cyclone IV GX
Logic Elements	109,424
Embedded Memory	5,621,760 bits
User I/O Pins	475
Embedded 18x18 Multipliers	156
PLLs	4
Transceiver Count	Up to 8
Transceiver Data Rate	Up to 3.125 Gbps
Process Technology	60 nm
Core Voltage	1.2 V
パッケージ	896-ball FBGA (F31)
Speed Grade	C6
動作温度	0C to +85C (commercial)
Configuration Modes	JTAG, AS, PPS
PCIe Hard IP	PCIe Gen1 x1/x2/x4
実装タイプ	Surface Mount (BGA)

EP4CGX110DF31C6N 896-ball fbga (f31) ピン配置ガイド

EP4CGX110DF31C6N (896-ball fbga (f31) パッケージ) のピン配置。このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

EP4CGX110DF31C6N の 896-ball fbga (f31) パッケージピン配置図

詳細なピン配置データはありません: EP4CGX110DF31C6N.

詳細はデータシートをご参照ください。

主な用途

EP4CGX110DF31C6N の用途: 6 件s: Industrial Machine Vision, Broadcast Video Processing, PCI Express Endpoint Card, Small-Cell Base Station CPRI Link, LVDS / Sub-LVDS Display Bridge, Multi-Protocol Wireline Bridge.

🏭

Industrial Machine Vision

The EP4CGX110DF31C6N's 109,424 logic elements, 156 embedded 18x18 multipliers, and 475 user IOs make it well suited for industrial machine vision pipelines running multiple Camera Link or CoaXPress frame-grabber channels. The 5,621,760 bits of embedded memory buffer full-HD image rows without external SRAM, while four PLLs derive pixel-clock domains from sensor LVDS inputs. Eight multi-gigabit transceivers at 3.125 Gbps drive GigE Vision or USB3 Vision uplinks to host PCs. Design tip: allocate a dedicated ground pour under the BGA and route LVDS pairs with 100 ohm differential impedance.

おすすめ

📺

Broadcast Video Processing

Broadcast video designs using SDI, HDMI, or DisplayPort benefit from the EP4CGX110DF31C6N's up to eight 3.125 Gbps transceivers, which can carry 3G-SDI or HDMI 1.4 TMDS streams with external PHY conditioning. 156 DSP blocks enable real-time scaling, deinterlacing, and color-space conversion, while 475 user IOs aggregate 24-bit RGB buses and parallel video interfaces. Quartus Prime supports free video IP cores for HDMI and SDI. Design tip: place AC-coupling caps within 5 mm of each transceiver ball and isolate the transceiver power island with a ferrite bead.

おすすめ

EP4CGX110DF31I7N · Intel

🖥️

PCI Express Endpoint Card

The EP4CGX110DF31C6N integrates a hard PCIe Gen1 IP block supporting x1, x2, or x4 lanes at 2.5 Gbps, eliminating external PHY ICs and reducing BOM cost. 109K logic elements implement the PCIe TLP/DLL state machine, BAR mapping, MSI-X interrupts, and customer application logic. Designers can prototype Gen1 endpoint cards on low-cost boards and migrate to Gen2 if higher throughput is needed. Design tip: the PCIe reference clock must be AC-coupled to the FPGA refclk pins; reference Intel AN 456 for board layout.

おすすめ

EP4CGX110DF31C7N · Intel

📡

Small-Cell Base Station CPRI Link

CPRI (Common Public Radio Interface) links between baseband units and remote radio heads run at 3.072 Gbps (CPRI option 6) or higher; the EP4CGX110DF31C6N's eight 3.125 Gbps transceivers comfortably handle four CPRI links plus an SFP+ uplink. 109K logic elements implement the CPRI framing, antenna-carrier mapping, and CPRI-to-Ethernet bridging. The 1.2 V core and 60 nm process deliver low standby power for outdoor small-cell deployments. Design tip: use separate analog and digital power rails and route reference clocks with controlled impedance.

おすすめ

EP4CGX110DF31I7N · Intel

📺

LVDS / Sub-LVDS Display Bridge

The EP4CGX110DF31C6N drives up to 475 LVDS or Sub-LVDS pairs, making it ideal for converting between legacy parallel LCD interfaces and modern MIPI DSI/CSI bridges. Designers use the PLL-driven LVDS SERDES to serialize 24/48-bit RGB buses onto a small number of twisted pairs, easing flex-cable routing. 156 multipliers accelerate color-space conversion and dithering. Design tip: match LVDS trace lengths to within 5 mil across each channel and add a common-mode choke near the connector.

おすすめ

EP4CE75F29C8N · Intel

🌐

Multi-Protocol Wireline Bridge

Protocol-bridging applications such as Serial RapidIO to Ethernet, PCIe to Aurora, or SGMII to RGMII benefit from the EP4CGX110DF31C6N's mix of transceivers and abundant logic. The device can implement two independent bridging channels simultaneously using only a fraction of the 109K logic budget, leaving room for on-chip packet buffering in 5,621,760 bits of embedded memory. Quartus Prime supports Serial RapidIO and SGMII soft-IP cores free of charge. Design tip: route each transceiver channel on its own ground-bordered microstrip to minimize crosstalk.

おすすめ

EP4CGX110DF31C7N · Intel

おすすめ製品の概要

EP4CGX110DF31C7N Intel 使用用途: Industrial Machine Vision, PCI Express Endpoint Card, Multi-Protocol Wireline Bridge EP4CE75F29C8N Intel 使用用途: Industrial Machine Vision, LVDS / Sub-LVDS Display Bridge EP4CGX110DF31I7N Intel 使用用途: Broadcast Video Processing, Small-Cell Base Station CPRI Link

What is the logic element count of EP4CGX110DF31C6N?

The EP4CGX110DF31C6N integrates 109,424 logic elements (LEs) in a Cyclone IV GX FPGA. According to the Intel Cyclone IV Device Handbook, each LE consists of a 4-input LUT, a register, and carry/control logic, and 16 LEs are grouped into a Logic Array Block (LAB). The same die provides 5,621,760 bits of embedded memory across M9K blocks.

How many transceivers does EP4CGX110DF31C6N support?

The EP4CGX110DF31C6N includes up to eight multi-gigabit transceivers operating at data rates up to 3.125 Gbps. According to the Intel Cyclone IV GX family datasheet, the channels support CPRI, PCIe Gen1, Serial RapidIO, and SGMII protocols and require AC-coupled backplanes with controlled impedance of 100 ohm differential.

What package does EP4CGX110DF31C6N use?

The EP4CGX110DF31C6N is housed in a 896-ball FineLine BGA (FBGA) package with the designator F31. According to the Intel Cyclone IV GX packaging specification, the package measures 31 mm x 31 mm with a 1.0 mm ball pitch, suitable for high-density designs that require controlled-impedance signal routing and extensive power/ground planes.

What is the operating temperature of EP4CGX110DF31C6N?

The EP4CGX110DF31C6N is rated for commercial temperature operation from 0C to +85C, as indicated by the "C" in the speed-grade suffix. According to the Cyclone IV GX datasheet, the "I" speed-grade variant (EP4CGX110DF31I6N) is required for industrial -40C to +100C operation, while the present part is intended for benign indoor environments.

Where to buy EP4CGX110DF31C6N online?

EP4CGX110DF31C6N is available through authorized Intel distributors including DigiKey, Mouser, and Arrow. According to distributor listings (as of 2026-09-10), the part is in active production and ships with 4-6 week lead time for production volumes. Spot-market availability is limited because Cyclone IV GX devices are not stocked by broad-line distributors.

What is the price of EP4CGX110DF31C6N?

EP4CGX110DF31C6N pricing as of 2026-09-10 starts around USD 285 per unit at 1-piece quantity. According to current distributor tier data, volume pricing drops to USD 175 per unit at 1000 pieces. The Cyclone IV GX family is positioned as Intel's lowest-cost transceiver FPGA, but list prices remain premium due to the 896-ball FBGA package and integrated SERDES channels.

What is the lead time for EP4CGX110DF31C6N?

Lead time for EP4CGX110DF31C6N is typically 4-6 weeks from authorized Intel distributors as of 2026-09-10. According to distributor inventory data, production-volume orders require booking against a forecast. Customers needing urgent samples can request them from the Intel FPGA Sample Service, subject to qualification.

Is EP4CGX110DF31C6N in stock?

EP4CGX110DF31C6N inventory fluctuates by distributor as of 2026-09-10. According to recent listings, distributor warehouse stock is limited (typically less than 100 pieces), so most orders are accepted against the 4-6 week factory lead time. Customers are advised to confirm current availability before committing design schedules.

EP4CGX110DF31C6N vs EP4CGX110DF31C7N - which is faster?

EP4CGX110DF31C6N uses the C6 speed grade while EP4CGX110DF31C7N uses the C7 speed grade; the C7 variant is faster. According to the Cyclone IV GX speed-grade table, C7 yields roughly 15 percent higher internal clock Fmax than C6 for the same logic utilization. Both share the same 896-ball F31 package and identical pinout, making C6 and C7 drop-in compatible from a board perspective.

What is the difference between EP4CGX110DF31C6N and EP4CGX150DF31C6N?

EP4CGX110DF31C6N provides 109,424 logic elements whereas EP4CGX150DF31C6N provides 149,760 logic elements - approximately 37 percent more logic capacity. According to the Cyclone IV GX family guide, both parts share the same 896-ball F31 FBGA package and pinout, enabling board reuse when migrating from -110 to -150 density. Embedded memory and transceiver counts also differ slightly.

When should I choose EP4CGX110DF31C6N over EP4CGX75DF31C6N?

Choose EP4CGX110DF31C6N when your design requires more than 75,000 logic elements or expanded memory capacity; EP4CGX110 offers 109,424 LEs versus EP4CGX75 at 73,920 LEs. According to the Cyclone IV GX datasheet, both share the same F31 896-ball FBGA package, allowing seamless board reuse when scaling up density. Select -110 only when the smaller device no longer fits your logic or memory budget.

What is the best drop-in replacement for EP4CGX110DF31C6N?

The best drop-in replacement for EP4CGX110DF31C6N is EP4CGX110DF31C7N from Intel - same 896-ball F31 FBGA package, pin-compatible, and 15 percent faster C7 speed grade. According to Intel Cyclone IV GX datasheets, both parts share identical logic, memory, and transceiver resources, so C7 can substitute C6 without any PCB or firmware changes other than Quartus recompile.

Can EP4CGX110DF31I7N replace EP4CGX110DF31C6N?

Yes, EP4CGX110DF31I7N can replace EP4CGX110DF31C6N with board-level drop-in compatibility. Both share the 896-ball F31 FBGA package and identical pinout, and the I7 variant offers both industrial -40C to +100C temperature range and a faster speed grade than C6. According to the Cyclone IV GX family guide, the higher temperature rating and speed grade are supersets of C6, so no board changes are required.

Where to download EP4CGX110DF31C6N datasheet PDF?

The EP4CGX110DF31C6N datasheet PDF is available from the official Intel Cyclone IV GX product page at https://www.altera.com/products/fpga/cyclone/iv/gx/ep4cgx110-f31. According to Intel documentation policy, the datasheet covers device features, electrical characteristics, and pinout but detailed board-layout guidelines reside in the Cyclone IV Device Handbook, available from the same portal.

Where to find EP4CGX110DF31C6N pinout?

The EP4CGX110DF31C6N pinout is documented in the Cyclone IV Device Handbook Pin Information chapter, available as PDF download from the Intel Cyclone IV GX support page. According to the handbook, the 896-ball F31 FBGA pinout is shared across all Cyclone IV GX F31-package variants, so the same pin table applies to EP4CGX110DF31I7N, EP4CGX110CF31C8N, and other F31-package siblings.

What is the Lattice Semiconductor equivalent for EP4CGX110DF31C6N?

The closest Lattice Semiconductor equivalent for EP4CGX110DF31C6N is the LFE5UM-85F-8BG554CES or ECP5-series family with similar logic density. According to Lattice product documentation, the ECP5 LFE5UM-85F provides 84K LUTs and multi-protocol SERDES in a BG554 package - close in resource count but NOT pin-compatible. A true drop-in board replacement requires a Lattice part in the same FBGA-896 footprint; Lattice does not currently produce a 896-ball part in that density, so cross-brand substitution typically requires PCB rework.

エンジニアリング参考データ: EP4CGX110DF31C6N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose EP4CGX110DF31C6N when your design needs integrated multi-gigabit transceivers (up to eight channels at 3.125 Gbps), a hard PCIe Gen1 endpoint controller, and roughly 100K logic elements in a single FPGA - all at the lowest cost point in Intel's transceiver-enabled Cyclone family. If you need only the logic resources without SERDES, step down to the Cyclone IV E family (e.g., EP4CE75F29C8N) and save roughly 30 percent on unit cost. If you exceed 100K LEs or need more memory bandwidth, step up to EP4CGX150DF31C6N in the same F31 package for seamless board reuse. For industrial -40C to +100C operation, use the I7 variant (EP4CGX110DF31I7N) instead of the commercial C6 device. For the absolute fastest timing closure, the C7 variant (EP4CGX110DF31C7N) is pin-compatible and roughly 15 percent faster.

代替品との比較

パラメータ	この製品	EP4CGX110DF31C7N	EP4CGX110DF31I7N	EP4CGX110DF27C8N	EP4CGX110CF23C7N	EP4CGX150DF31C6N	EP4CE75F29C8N
Brand	Intel	Intel	Intel	Intel	Intel	Intel	Intel
Package	896-ball FBGA (F31)	896-ball FBGA (F31) - same	896-ball FBGA (F31) - same	FBGA-672 (F27) - different	FBGA-484 (F23) - different	896-ball FBGA (F31) - same	FBGA-780 (F29) - different
Logic Elements	109,424	109,424	109,424	109,424	109,424	149,760	78,400 (Cyclone IV E)
Speed Grade	C6	C7 (faster)	I7 (industrial, faster)	C8	C7	C6	C8
Operating Temperature	0C to +85C (commercial)	0C to +85C (commercial)	-40C to +100C (industrial)	0C to +85C (commercial)	0C to +85C (commercial)	0C to +85C (commercial)	0C to +85C (commercial)
Embedded Memory (bits)	5,621,760	5,621,760	5,621,760	5,621,760	5,621,760	6,480,000	3,063,552 (Cyclone IV E)
User I/O Pins	475	475	475	380	290	475	488
Transceiver Count	8 (up to 3.125 Gbps)	8	8	8	4	8	0 (Cyclone IV E, no transceivers)
Core Voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V

主な差別化要因

Integrated 3.125 Gbps transceivers （vs EP4CE75F29C8N)
Hard PCIe Gen1 controller （vs EP4CE75F29C8N)
Higher density than Cyclone IV E mid-range （vs EP4CE75F29C8N)

設計ノート

Estimated: the EP4CGX110DF31C6N draws approximately 1.5 A to 3.5 A from the 1.2 V VCCINT rail and 0.3 A to 1.5 A from each VCCIO bank, depending on toggle rate and utilization. Decouple VCCINT with 4 x 10 uF bulk + 40 x 100 nF ceramics distributed under the BGA, and place 4 x 4.7 uF per VCCIO bank. Provide separate analog VCCAUX and VCCA_PLL rails each decoupled with 100 nF and 10 uF. Use Intel PowerPlay early-power-estimator to refine your budget before sign-off.

Estimated: the 896-ball F31 FBGA uses 1.0 mm ball pitch and a 31 mm x 31 mm body. Microvia (0.1 mm) stack-up is mandatory, and at least one full PCB layer pair should be dedicated to power/GND with the VCCINT island poured continuously under the die. Maintain 100 ohm differential impedance on transceiver pairs, with intra-pair skew below 5 mil. Reference Intel AN 456 for the full Cyclone IV GX high-speed-layout checklist.

Estimated: each multi-gigabit transceiver channel should be AC-coupled with 100 nF caps within 5 mm of the FPGA ball, and reference clocks must be AC-coupled to dedicated refclk pins. Use IBIS-AMI simulations (HSPICE) for critical 3.125 Gbps links, especially backplane applications where insertion-loss budgets of 10 to 15 dB apply at the Nyquist frequency.

Common pitfalls include: (1) omitting the JTAG pull-up on TCK/TMS, which prevents configuration; (2) leaving MSEL pins floating, which selects the wrong configuration mode; (3) under-estimating configuration flash write cycles - use a 16 Mb or larger SPI flash for AS mode; (4) not providing proper POR sequencing - assert nCONFIG after all rails are stable for at least 1 ms. Reference the Cyclone IV Device Handbook chapter 10 for the full configuration checklist.

コンプライアンス情報

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

鉛フリー

Yes

ハロゲンフリー

Yes

紛争鉱物

Compliant

RoHS and REACH compliance per Intel product page; not AEC-Q100 qualified (FPGAs are not typically AEC-Q100 unless specified). Halogen-free per JEDEC JS709.

データ検証日: 2026-09-10 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

出典: Manufacturer Product Page, Manufacturer Datasheet, Distributor, Distributor, Distributor