EP910PI-25T - 24-Macrocell Classic EPLD, 25ns, DIP-40 | Altera
部品番号: EP910PI-25T ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910PI-25T 概要
A Classic EPLD (Erasable Programmable Logic Device) is a type of programmable logic that belongs to the broader hierarchy of programmable logic devices (PLDs), sitting above discrete SSI/MSI logic gates and below modern CPLDs and FPGAs in integration density. EP910-family EPLDs were designed for high-speed combinatorial and registered logic replacement where the application requires deterministic, fixed-pin timing that an FPGA cannot guarantee.
The EP910 integrates a programmable AND/OR array, 24 flip-flop-equipped macrocells, and a flexible interconnect scheme, giving designers 38 dedicated input pins and 24 I/O pins. Per the manufacturer datasheet, the EP910 offers typical CMOS static power consumption below 100 mW and operates from a single 5V supply, making it suitable for both battery-backed and line-powered industrial systems.
Architecturally, the EP910 uses Altera's Classic MAX-like AND/OR structure with UV-erasable EPROM cells for programming; the "PI" suffix denotes plastic DIP packaging, "-25" denotes the 25 ns pin-to-pin propagation delay (tpd), and the "T" suffix denotes tape-and-reel packaging for high-volume assembly.
Typical applications include industrial control glue logic, address decoding for microprocessor systems, state-machine implementation, bus-interface and arbitration logic, and legacy replacement of discrete 74LS TTL logic. The 40-pin DIP form factor supports both through-hole PCB assembly and socketed prototyping on breadboards and development systems.
Design consideration: the EP910 uses a single +5V VCC supply; designers must observe the 25 ns tpd budget when targeting bus-cycle or memory-interface timings. For new designs, designers should evaluate whether a modern CPLD such as Altera MAX V or Lattice ispMACH 4000 offers better cost-per-gate; however, the EP910 remains in service in long-lifecycle industrial, military and avionics systems.
This page synthesizes current distributor stock, same-family drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: EP910PI-25T — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910PI-25T （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCC), Technology, Family, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP910PI-25
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EP910PI-20T
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP910PI-15T
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EP910PI-20
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EP910PI-12T
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP910PI-25T 最大定格＆電気的特性
| Family | Altera Classic EPLD Family |
| Macrocells | 24 |
| Equivalent Gates | 900 (SSI/MSI equivalent) |
| Maximum Inputs | 36 |
| Maximum Outputs | 24 |
| Propagation Delay (tpd) | 25 ns |
| Supply Voltage (VCC) | 5 V |
| Technology | CMOS, UV-erasable EPROM |
| パッケージ | 40-pin PDIP (600-mil) |
| Programming | UV-erasable |
| 実装タイプ | Through-Hole (DIP) |
| Static Power | <100 mW (typical CMOS) |
EP910PI-25T ピン構成
| ピン 1 | I/O — Bidirectional I/O pin (macrocell 1) |
| ピン 2 | I/O — Bidirectional I/O pin (macrocell 2) |
| ピン 3 | I/O — Bidirectional I/O pin (macrocell 3) |
| ピン 4 | I/O — Bidirectional I/O pin (macrocell 4) |
| ピン 5 | I/O — Bidirectional I/O pin (macrocell 5) |
| ピン 6 | I/O — Bidirectional I/O pin (macrocell 6) |
| ピン 7 | I/O — Bidirectional I/O pin (macrocell 7) |
| ピン 8 | I/O — Bidirectional I/O pin (macrocell 8) |
| ピン 9 | I/O — Bidirectional I/O pin (macrocell 9) |
| ピン 10 | I/O — Bidirectional I/O pin (macrocell 10) |
| ピン 11 | I/O — Bidirectional I/O pin (macrocell 11) |
| ピン 12 | I/O — Bidirectional I/O pin (macrocell 12) |
| ピン 13 | I/O — Bidirectional I/O pin (macrocell 13) |
| ピン 14 | I/O — Bidirectional I/O pin (macrocell 14) |
| ピン 15 | I/O — Bidirectional I/O pin (macrocell 15) |
| ピン 16 | I/O — Bidirectional I/O pin (macrocell 16) |
| ピン 17 | I/O — Bidirectional I/O pin (macrocell 17) |
| ピン 18 | I/O — Bidirectional I/O pin (macrocell 18) |
| ピン 19 | I/O — Bidirectional I/O pin (macrocell 19) |
| ピン 20 | VCC — +5V supply voltage |
| ピン 21 | I/O — Bidirectional I/O pin (macrocell 20) |
| ピン 22 | I/O — Bidirectional I/O pin (macrocell 21) |
| ピン 23 | I/O — Bidirectional I/O pin (macrocell 22) |
| ピン 24 | I/O — Bidirectional I/O pin (macrocell 23) |
| ピン 25 | I/O — Bidirectional I/O pin (macrocell 24) |
| ピン 26 | INPUT — Dedicated input pin |
| ピン 27 | INPUT — Dedicated input pin |
| ピン 28 | INPUT — Dedicated input pin |
| ピン 29 | INPUT — Dedicated input pin |
| ピン 30 | INPUT — Dedicated input pin |
| ピン 31 | INPUT — Dedicated input pin |
| ピン 32 | INPUT — Dedicated input pin |
| ピン 33 | INPUT — Dedicated input pin |
| ピン 34 | INPUT — Dedicated input pin |
| ピン 35 | INPUT — Dedicated input pin |
| ピン 36 | INPUT — Dedicated input pin |
| ピン 37 | INPUT — Dedicated input pin |
| ピン 38 | INPUT — Dedicated input pin |
| ピン 39 | GND — Ground |
| ピン 40 | NC — Not connected (per datasheet pinout) |
主な用途
EP910PI-25T の用途: 6 件s: Industrial Glue Logic Replacement, Microprocessor Address Decoding, State-Machine Implementation, Bus Interface and Arbitration Logic, Legacy TTL Logic Replacement, Avionics and Military Embedded Systems.
Industrial Glue Logic Replacement
The EP910PI-25T's 24 macrocells and 900 equivalent gates make it ideal for replacing clusters of 74LS TTL glue logic in legacy industrial controllers. With 36 inputs and 24 outputs in a 40-pin DIP package, a single EP910 consolidates address decoding, bus arbitration and interrupt-priority logic that previously required a half-dozen SSI/MSI packages. The 25 ns tpd comfortably meets 8 MHz and most 12 MHz microprocessor bus-cycle budgets, while CMOS static power under 100 mW keeps thermal dissipation low inside sealed industrial enclosures. Engineers should budget tpd across combinational paths and clock-to-output delays.
おすすめ
Microprocessor Address Decoding
The EP910PI-25T excels at generating chip-select and memory-map decode signals for 8-bit and 16-bit microprocessor systems. Its 36 dedicated inputs are sufficient to decode 24-bit address buses plus control signals like /RD, /WR and /MREQ. The 24 outputs drive peripheral chip-enable lines directly, eliminating one or two layers of 74LS138/139 decoder trees. The 40-pin PDIP package supports socketed prototyping on retro SBCs, while the 25 ns tpd accommodates 8 MHz 8086/68k bus cycles. Compare with EP910PI-15T (15 ns) when higher bus-clock headroom is needed.
おすすめ
State-Machine Implementation
The EP910PI-25T's 24 macrocells provide ample D-flip-flop capacity for medium-complexity state machines such as communication-protocol controllers, sequencers and custom bus masters. Each macrocell offers product-term-driven clock, reset and preset, supporting both Moore and Mealy machine topologies. The Classic EPLD architecture guarantees deterministic, fixed-pin propagation delays, which is critical for asynchronous or safety-related state machines that cannot tolerate FPGA routing jitter. Pin-to-pin tpd of 25 ns supports state-transition frequencies up to ~20 MHz; the EP910PI-15T (15 ns) covers faster protocols.
おすすめ
Bus Interface and Arbitration Logic
The EP910PI-25T serves as a flexible bus-interface and arbiter for multi-master systems, supporting DMA handshake, interrupt priority and wait-state insertion in a single device. Its 36 inputs handle address, command and request lines from multiple bus masters, while 24 outputs drive grant lines, ready signals and peripheral enables. With 5V CMOS supply and sub-100 mW static power, the EP910 is ideal for VME, ISA and proprietary backplane designs that need low-power, deterministic logic. Use the EP910PI-15T (15 ns) for high-speed backplane applications requiring tighter arbitration timing.
おすすめ
Legacy TTL Logic Replacement
The EP910PI-25T consolidates 30-60 discrete 74LS00/74LS74/74LS138/74LS245 packages into a single 40-pin DIP, reducing PCB area, power consumption and assembly cost in legacy product refreshes. With 900 equivalent gates and 24 flip-flops, it covers most small-to-medium decoder/encoder/latch designs found in test equipment and instrumentation. The Classic EPLD UV-EPROM programming supports field firmware updates using standard Altera programming tools, while CMOS static power under 100 mW helps meet energy-budget targets in retrofits.
おすすめ
Avionics and Military Embedded Systems
The EP910PI-25T is widely deployed in long-lifecycle avionics and military embedded systems where the Classic EPLD family's deterministic timing and radiation tolerance have been qualified over decades. Ceramic DIP variants such as EP910DM/883B or EP910DM883B provide MIL-STD-883 processing for defense applications; the plastic EP910PI-25T serves commercial and industrial avionics subsystems. Designers should review DSCC and DLA drawings for the exact 883B variant; the EP910PI-25T in tape-and-reel format is suitable for high-volume avionics LRUs and military communication equipment.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910PI-25T — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910PI-25 | EP910PI-20T | EP910PI-15T | EP910PI-20 | EP910PI-12T |
|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tpd) | 25 ns | 25 ns | 20 ns | 15 ns | 20 ns | 12 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Equivalent Gates | 900 | 900 | 900 | 900 | 900 | 900 |
| Maximum Inputs | 36 | 36 | 36 | 36 | 36 | 36 |
| Maximum Outputs | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Packaging Format | Tape & Reel | Tube | Tape & Reel | Tape & Reel | Tube | Tape & Reel |
主な差別化要因
- Tape-and-reel packaging for high-volume assembly （vs EP910PI-25)
- 25 ns tpd standard speed grade balance （vs EP910PI-20T)
- Plastic DIP package vs ceramic/PLCC variants （vs EP910DM883B)
設計ノート
The EP910PI-25T's 40-pin PDIP package uses a 600-mil row spacing, which is the standard 0.6" wide DIP footprint. Decoupling: place a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 20) and the GND pin (pin 39); add a bulk 10 µF tantalum or aluminum electrolytic capacitor at the board's power-entry point. Keep TTL/CMOS switching traces away from the dedicated input pins (26-38) to minimize crosstalk on asynchronous inputs. Use a ground plane under the device to reduce EMI.
Do not confuse EP910PI-25T (plastic DIP, 25 ns) with the EP910DM/883B or EP910DM883B (ceramic MIL-STD-883 qualified) variant - the ceramic part is for defense applications only and is significantly more expensive. Also note that the EP910 family is OBSOLETE; sourcing from authorized distributors is critical to avoid counterfeit parts. Always verify that the programmed JEDEC file matches the original design intent before deployment.
The EP910PI-25T's 24 macrocells are organized as I/O banks; group related I/O signals on adjacent pins to simplify PCB routing and minimize trace congestion. The 36 dedicated inputs (pins 26-38) are suitable for high-impedance buses and should be pulled up/down through 10 kohm resistors if left unused to prevent floating-input noise. Leave pin 40 (NC) floating or tied to GND per the datasheet recommendation.
コンプライアンス情報
The Altera Classic EPLD family was designed before RoHS directives took full effect; RoHS/REACH compliance status for the EP910PI-25T is not documented in the available data. The EP910DM/883B and EP910DM883B ceramic variants are MIL-STD-883 processed but not AEC-Q100 qualified (not an automotive grade).
