EPC20LI20N - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel/Altera
部品番号: EPC20LI20N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $23.54 | $23.54 |
| 10 | $22.18 | $221.80 |
| 100 | $20.42 | $2,042.00 |
| 500 | $18.86 | $9,430.00 |
| 1,000 | $17.5 | $17,500.00 |
EPC20LI20N 概要
An FPGA configuration PROM is a non-volatile memory device that stores the FPGA's bitstream and serially transfers it to the FPGA at power-up or reconfiguration. The hierarchy is: configuration PROM -> non-volatile memory -> serial flash memory -> semiconductor memory -> integrated circuit. In the system power-on sequence, the PROM presents the configuration bitstream on the FPGA's DATA0/DCLK/nCONFIG/nSTATUS lines, after which the PROM enters standby with negligible current draw. This category of device is critical for SRAM-based FPGAs because the LUTs and routing fabric are volatile and must be reloaded on every power cycle.
Key features of the EPC20LI20N include 1.6 Mbit (approximately 200 Kbyte) of storage organized as 65,536 x 1-bit words, in-system programmability through IEEE 1532/JTAG, an industry-standard 4-pin serial interface, low-power CMOS operation, and a guaranteed 10 MHz configuration clock rate. The 20-pin PLCC package is a JEDEC-standard footprint compatible with socketed programming and field replacement.
The EPC20LI20N's 1.6 Mbit density aligns with the bitstream sizes of mid-complexity Altera FPGAs such as APEX 20K and ACEX 1K devices. The 4-pin interface (DCLK, DATA0, nCONFIG, nSTATUS) is the legacy Altera Passive Serial (PS) configuration scheme, distinct from the newer Fast Passive Parallel (FPP) or Active Serial (AS) schemes used by EPCS or EPCQ devices.
Typical applications include factory-configuration of APEX 20K / ACEX 1K FPGA development boards, industrial motion-control FPGA cards, telecom line-card bitstream storage, and legacy system maintenance where the original Altera-era configuration architecture must be preserved. For new designs, designers typically migrate to EPCS-series (Active Serial flash) configuration devices.
When designing with this part, ensure that the PROM-to-FPGA daisy-chain length and the 10 MHz clock limit are observed. Multi-device configuration chains require the nCASC pin to be wired between PROMs, and the PROM's VCC decoupling must use a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin.
This page synthesizes distributor pricing, drop-in alternatives, and practical configuration-design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: EPC20LI20N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC20LI20N （同一形状・フットプリント） — 相違点: Mounting Type, Memory Type, Memory Size, Package, Configuration Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPC2LI20N
✅ ドロップイン✓ 在庫あり
$5.1 / 個
データシートを見る →EPC1LI20N
✅ ドロップイン✓ 在庫あり
$7.8 / 個
データシートを見る →EPC2LI20
✅ ドロップイン✓ 在庫あり
$5.95 / 個
データシートを見る →EPC1LC20
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EPC20LC20U
✅ ドロップイン✓ 在庫あり
$8.2 / 個
データシートを見る →EPC20LI20N 最大定格＆電気的特性
| メモリタイプ | EPROM (UV-erasable, in-system programmable) |
| メモリサイズ | 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) |
| インターフェース | Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) |
| 電源電圧 | 3.3 V (5.0 V compatible variant in same family) |
| Configuration Clock | Up to 10 MHz |
| Target FPGA Families | APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| パッケージ | 20-pin PLCC (9x9 mm, JEDEC MS-018) |
| 実装タイプ | Surface Mount (PLCC socket or direct solder) |
| Programming Interface | IEEE 1532 / JTAG (in-system) |
| 動作温度 | -40C to +85C (industrial) |
| Multi-Device Daisy-Chain | Supported via nCASC pin |
EPC20LI20N ピン構成
| ピン 1 | DCLK — Configuration clock input to FPGA (10 MHz max) |
| ピン 2 | DATA0 — Serial data output to FPGA |
| ピン 3 | nCONFIG — Configuration control input from FPGA (active low) |
| ピン 4 | nSTATUS — Configuration status output to FPGA (active low) |
| ピン 5 | OE/nCE — Output enable / chip enable input (active low) |
| ピン 6 | nCASC — Cascade output for multi-device daisy chain (active low) |
| ピン 7 | VCC — 3.3 V supply voltage |
| ピン 8 | VPP — Programming voltage supply (factory programming) |
| ピン 9 | GND — Ground |
| ピン 10 | GND — Ground |
| ピン 11 | TDI — JTAG test data input (IEEE 1532 programming) |
| ピン 12 | TMS — JTAG test mode select |
| ピン 13 | TCK — JTAG test clock |
| ピン 14 | TDO — JTAG test data output |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | GND — Ground |
主な用途
EPC20LI20N の用途: 6 件s: APEX 20K FPGA Configuration, ACEX 1K FPGA Bitstream Storage, Legacy FLEX 10K Maintenance Card, Mercury FPGA Development Platform, Industrial Control PLCC-Based Logic Replacement, Multi-Device FPGA Daisy-Chain Boot Storage.
APEX 20K FPGA Configuration
The EPC20LI20N is the reference Altera configuration device for the APEX 20K family, providing the 1.6 Mbit density required to store mid-complexity APEX 20K bitstreams. The PROM sits on the board and streams configuration data into the FPGA's DATA0/DCLK/nCONFIG/nSTATUS pins at 10 MHz, completing the load in roughly 160 ms for a fully populated APEX 20K. The 4-pin Passive Serial interface is simple to wire and survives multi-device daisy-chains via nCASC, which allows two PROMs to support APEX 20KE bitstreams larger than 1.6 Mbit. Place a 0.1 uF decoupling capacitor within 5 mm of the VCC pin.
おすすめ
ACEX 1K FPGA Bitstream Storage
ACEX 1K FPGAs require between 0.5 and 1 Mbit of configuration storage, well within the 1.6 Mbit capacity of the EPC20LI20N. The PROM's industrial -40C to +85C rating matches the operating envelope of factory-floor ACEX 1K cards used in motion control and machine vision. Designers typically leave 50% of the PROM unused for future firmware revisions. The Passive Serial interface is simple to integrate and uses only four FPGA pins, leaving more user I/O available than Active Serial schemes.
おすすめ
Legacy FLEX 10K Maintenance Card
Many telecom and industrial control cards built in the late 1990s use FLEX 10KE or FLEX 10KA FPGAs that depend on the EPC2 family of configuration PROMs. The EPC20LI20N provides a drop-in replacement that maintains the original Passive Serial configuration path. As of 2026-09-11, the part is NRND, so field-replacement cards should be qualified with the EPC2LI20N variant to ensure continuity. The PROM's industrial temperature rating and 20-pin PLCC socket compatibility simplify field swaps.
おすすめ
Mercury FPGA Development Platform
Altera's Mercury family of FPGAs (EP1M series) is configured via the same Passive Serial interface as APEX 20K, and the EPC20LI20N provides the bitstream storage. Mercury's high-speed serial transceivers require deterministic power-up sequencing, which the PROM's nCONFIG/nSTATUS handshake provides. For Mercury designs, the 1.6 Mbit density covers all bitstream sizes in the Mercury family. The 20-pin PLCC package is socket-compatible with the original Altera development board reference design.
おすすめ
Industrial Control PLCC-Based Logic Replacement
Some long-lifecycle industrial controllers still rely on Altera PLCC-packaged configuration PROMs because the PLCC socket allows field replacement without desoldering. The EPC20LI20N's industrial temperature rating, JEDEC-standard 9x9 mm PLCC outline, and 20-year Altera legacy support make it suitable for these sockets. Replacement requires verifying that the new bitstream fits within 1.6 Mbit and that the supply rail matches the 3.3 V VCC specification.
おすすめ
Multi-Device FPGA Daisy-Chain Boot Storage
When two FPGAs are daisy-chained on the same board, both can be configured from a single EPC20LI20N if the combined bitstream fits within 1.6 Mbit. Otherwise, two PROMs are cascaded via the nCASC pin, where the second PROM's nCASC output drives the first PROM's nCE. According to the Altera datasheet, this scheme supports APEX 20KE devices with bitstreams up to 3.2 Mbit. The 10 MHz Passive Serial clock is shared between all PROMs in the chain, ensuring synchronous configuration across all FPGAs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC20LI20N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC2LI20N | EPC1LI20N | EPC2LI20 | EPC1LC20 | EPC20LC20U |
|---|---|---|---|---|---|---|
| Package | 20-PLCC (9x9 mm) | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1 Mbit | 1.6 Mbit | 1 Mbit | 1.6 Mbit |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C |
| Configuration Clock | 10 MHz max | 10 MHz max | 10 MHz max | 10 MHz max | 10 MHz max | 10 MHz max |
| Interface | Passive Serial (4-pin) | Passive Serial (4-pin) | Passive Serial (4-pin) | Passive Serial (4-pin) | Passive Serial (4-pin) | Passive Serial (4-pin) |
| Target FPGA Family | APEX 20K/KC/KE, ACEX 1K, FLEX 10K, Mercury | Same families | Same families (smaller bitstreams) | Same families | Same families (smaller bitstreams) | Same families |
| Daisy-Chain Support | Yes (nCASC pin) | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- 1.6 Mbit density supports full APEX 20K bitstreams （vs EPC1LI20N)
- Industrial temperature rating -40C to +85C （vs EPC2LI20)
- Drop-in compatibility with the entire EPC2 family footprint （vs EPC1LC20)
設計ノート
Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the EPC20LI20N's VCC pin (pin 7). According to Altera reference designs, an additional 10 uF tantalum bulk capacitor on the same VCC net suppresses voltage transients during PROM-to-FPGA configuration switching. Ground pins 9, 10, and 20 should connect to a single ground plane with short traces; do not place signal traces between these GND pins because the return-current path would be disrupted and cause configuration errors.
The DCLK and DATA0 traces between the EPC20LI20N and the target FPGA should be length-matched to within 50 mils (1.27 mm) and kept under 4 inches (100 mm). According to the Altera Configuration Devices datasheet, longer traces can cause signal-integrity issues at the 10 MHz configuration clock, leading to configuration failures or CRC errors. Route these traces over a continuous ground plane and avoid crossing any switching-power signals. Place a 33 ohm series resistor near the FPGA's DCLK pin if the trace exceeds 2 inches.
Do not confuse the EPC20LI20N (1.6 Mbit, industrial temperature) with the EPC1LI20N (1 Mbit, industrial) or EPC2LI20 (1.6 Mbit, commercial temperature). The '20' vs '2' suffix in some listings refers to the same Altera family but may indicate density variations; always verify the bitstream fits before substitution. The 'N' suffix denotes lead-free termination. According to the Altera datasheet, an undersized PROM will silently fail to load the FPGA and the FPGA's CONF_DONE pin will never assert high. Always size the PROM to at least 110% of the compressed bitstream.
コンプライアンス情報
RoHS compliance per Intel/Altera product page for the EPC2 family. The 'N' suffix denotes lead-free Pb-free termination. Halogen-free status not explicitly listed in the verified data; consult Intel product compliance documents for confirmation. Not AEC-Q100 qualified - automotive applications should use a different configuration device.
