EPC1LC20 - 1Mb SRAM FPGA Config Memory, 20-PLCC | Intel / Altera
部品番号: EPC1LC20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.85 | $985.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.95 | $7,950.00 |
EPC1LC20 概要
An FPGA configuration memory, sometimes called a configuration PROM or bitstream loader, is a non-volatile storage device that holds the binary configuration data for SRAM-based LUT devices. Because SRAM FPGAs lose their configuration when power is removed, an external boot source must reload the bitstream at every power-up. Within the system hierarchy, the EPC1LC20 sits between the system's non-volatile storage and the FPGA's configuration logic, classified as an EEPROM-based configuration PROM in the broader category of memory ICs, falling under configuration PROMs for FPGAs in the Intel/Altera ecosystem.
Key features include 1,048,576 bits (1Mb) of serial Flash/EPROM configuration storage, 5.0V and 3.3V in-system programmability, JTAG-based ISP support, a dedicated serial configuration interface, and a multi-device configuration daisy-chain option. The PLCC-20 surface-mount package is footprint-compatible with the older EPC1PC8 (DIP-8) adapter boards when used with a socketed carrier.
The EPC1LC20 implements a synchronous serial interface with a 4-pin protocol (nCS, DCLK, DATA, nINIT_CONF) plus JTAG pins (TCK, TMS, TDI, TDO) for ISP. The internal architecture separates the JTAG controller, the configuration shift register, and the non-volatile memory array, allowing concurrent ISP and configuration read operations in many usage scenarios.
Typical applications include Altera ACEX 1K, APEX 20K, Cyclone, FLEX 10K, and Mercury family FPGA configuration storage; industrial control systems requiring remote bitstream updates via JTAG; legacy telecom and test equipment upgrades; and embedded prototypes migrating from older PROMs to in-system reprogrammable storage.
When designing with this device, ensure that the JTAG chain is terminated correctly and that nINIT_CONF is pulled to the correct logic level for the target FPGA family. The 8 MHz DCLK ceiling must be respected for the specific Altera FPGA being configured - some newer families require the companion EPC2 or EPC4 configuration devices instead.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPC1LC20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC1LC20 （同一形状・フットプリント） — 相違点: Package, Memory Type, Mounting Type, Compatible FPGA Families, Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPC1LC20N
✅ ドロップイン✓ 在庫あり
$8.4 / 個
データシートを見る →EPC1441LC20
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPC1LC120
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.3 / 個
データシートを見る →EPC1L20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.75 / 個
データシートを見る →EPC1L120
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.2 / 個
データシートを見る →EPC1LC20 最大定格＆電気的特性
| メモリタイプ | Non-volatile configuration memory (Flash/EPROM) |
| Memory Capacity | 1 Mbit (1,048,576 bits) |
| インターフェースタイプ | Serial configuration interface |
| Maximum DCLK Frequency | 8 MHz |
| 電源電圧 | 3.3 V or 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | 5.0 V and 3.3 V ISP |
| Configuration Mode | Serial, multi-device daisy-chain capable |
| パッケージ | 20-pin PLCC (J-leaded, surface mount) |
| ピン数 | 20 |
| 実装タイプ | Surface Mount |
| Compatible FPGA Families | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| JTAG Pins | TCK, TMS, TDI, TDO |
EPC1LC20 ピン構成
| ピン 1 | TMS — JTAG Test Mode Select input |
| ピン 2 | TCK — JTAG Test Clock input (also DCLK during configuration) |
| ピン 3 | TDI — JTAG Test Data In |
| ピン 4 | TDO — JTAG Test Data Out |
| ピン 5 | nCS — Chip Select (active low) for configuration interface |
| ピン 6 | DCLK — Configuration clock (shared with TCK during ISP) |
| ピン 7 | DATA — Serial configuration data output to FPGA |
| ピン 8 | nINIT_CONF — Configuration init control (active low) |
| ピン 9 | VCC — Power supply (3.3V or 5V) |
| ピン 10 | GND — Ground |
| ピン 11 | NC — Not connected (per datasheet) |
| ピン 12 | NC — Not connected (per datasheet) |
| ピン 13 | NC — Not connected (per datasheet) |
| ピン 14 | NC — Not connected (per datasheet) |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | OE — Output enable for DATA line |
| ピン 18 | nSTATUS — Configuration status indicator (active low) |
| ピン 19 | CONFIG_DONE — Configuration complete indicator |
| ピン 20 | VCC — Power supply (3.3V or 5V) |
主な用途
EPC1LC20 の用途: 6 件s: ACEX 1K / APEX 20K FPGA Configuration Storage, FLEX 10K Family FPGA Boot Source, Industrial Control System Remote Firmware Update, Legacy Telecom Equipment Bitstream Reload, Test & Measurement Instrumentation FPGA Loading, Embedded Prototype Development Board Configuration.
ACEX 1K / APEX 20K FPGA Configuration Storage
The EPC1LC20 is the legacy Altera-recommended configuration memory for ACEX 1K and APEX 20K SRAM-based LUT devices, whose bitstreams fit within the part's 1-Mbit capacity. Connecting to the FPGA via the 4-pin serial protocol (nCS, DCLK, DATA, nINIT_CONF), it reloads the configuration at every power-up using the 8 MHz DCLK ceiling, ensuring deterministic FPGA boot in industrial and telecom equipment. JTAG ISP via TCK/TMS/TDI/TDO enables remote field updates without removing the device from the board.
おすすめ
FLEX 10K Family FPGA Boot Source
The EPC1LC20 historically served as the boot PROM for Altera FLEX 10KE and FLEX 10KA devices, providing non-volatile storage for bitstreams up to 1 Mbit. Mounted in a 20-pin PLCC, it streams configuration data over the dedicated serial bus at DCLK rates up to 8 MHz, enabling sub-second FPGA boot in legacy designs. Multi-device daisy-chaining via nCS cascading allows multiple FPGAs to share a single EPC1LC20 chain, useful in factory automation controllers.
おすすめ
Industrial Control System Remote Firmware Update
Industrial PLCs and motor controllers using Altera FPGAs can use the EPC1LC20's JTAG-based in-system programmability to deliver remote firmware updates without physical access to the board. Operating at 3.3V or 5V, the EPC1LC20 receives a new bitstream over the JTAG chain and stores it internally, ready for the next power-up cycle. This makes it a strong fit for factory automation lines where downtime for firmware flash is unacceptable.
おすすめ
Legacy Telecom Equipment Bitstream Reload
Telecom base-station and switching equipment built around Altera APEX 20K and FLEX 10K FPGAs continues to rely on the EPC1LC20 for configuration storage. Its 1-Mbit capacity supports older protocol stacks, and its PLCC-20 surface-mount package suits the dense backplane layouts typical of legacy telecom racks. The 8 MHz DCLK rate ensures configuration completes within telecom-grade boot time budgets.
おすすめ
Test & Measurement Instrumentation FPGA Loading
Oscilloscopes, logic analyzers, and signal generators from the late 1990s and early 2000s frequently used Altera FPGAs paired with the EPC1LC20 to store calibration and DSP configuration bitstreams. The 20-pin PLCC socket allows field replacement when migrating to a new FPGA revision. The 3.3V/5V dual supply support enables direct integration with both TTL and CMOS logic families common in test instruments.
おすすめ
Embedded Prototype Development Board Configuration
Hobbyist and embedded prototype boards targeting older Altera development kits (e.g., ACEX 1K starter boards) use the EPC1LC20 to provide non-volatile configuration without requiring the user to manually program the FPGA each power-up. The PLCC-20 socket is durable for repeated prototype cycles and supports ISP via JTAG for rapid design iteration. Newer Altera FPGAs require the EPCQ family, but the EPC1LC20 remains the canonical boot source for ACEX/APEX-era boards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC1LC20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC1LC20N | EPC1441LC20 | EPC1LC120 | EPC1L20 | EPC1L120 |
|---|---|---|---|---|---|---|
| Package | 20-pin PLCC | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Memory Capacity | 1 Mbit | 1 Mbit | ~0.5 Mbit (smaller) | 1 Mbit | < 1 Mbit (lower density) | < 1 Mbit (industrial grade) |
| Supply Voltage | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V |
| Maximum DCLK | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Compatible FPGA Families | ACEX 1K, APEX 20K, FLEX 10K | ACEX 1K, APEX 20K, FLEX 10K | ACEX 1K, APEX 20K (smaller bitstream) | ACEX 1K, APEX 20K, FLEX 10K | FLEX 10K (smaller bitstream) | FLEX 10K (industrial) |
主な差別化要因
- Higher bitstream capacity than the EPC1441LC20 （vs EPC1441LC20)
- 20-pin PLCC surface-mount package （vs EPC1PC8 / EPC1PI8N (8-pin PDIP/PDIP through-hole))
- Dual-voltage ISP support (3.3V and 5V) （vs EPCQ-series modern configuration PROMs)
設計ノート
Place the EPC1LC20 within 50 mm of the target FPGA's configuration pins to minimize trace capacitance on the 8 MHz DCLK and DATA lines. Per Altera reference designs, the 20-pin PLCC socket should be socketed (not soldered) on prototype boards to enable easy migration between EPC1LC20, EPC1LC20N, and EPC1441LC20 variants. Add a 0.1 µF decoupling capacitor within 3 mm of each VCC pin (pins 9 and 20), and a single bulk 10 µF tantalum or ceramic near the package.
The DCLK line carries up to 8 MHz square-wave content with fast edge rates; route it as a 50-ohm controlled-impedance trace on inner layers if possible, and keep DATA trace length matched within 25 mm of DCLK to avoid setup-time violations on the target FPGA. Pull nCS high through a 4.7 kΩ resistor to VCC to prevent spurious configuration reads during FPGA JTAG operations. The JTAG signals (TCK, TMS, TDI, TDO) should be guarded with ground vias on both sides of the traces.
Do not use the EPC1LC20 with newer Altera FPGA families that require active-low configuration protocols or higher DCLK rates (e.g., Cyclone III, Stratix III, or later). These families require the EPCQ-series configuration devices. Also avoid tying nINIT_CONF to ground continuously - this latches the EPC1LC20 into ISP mode and prevents normal configuration. Verify that the bitstream file size does not exceed 1 Mbit; otherwise the FPGA will fail to configure with CONFIG_DONE never asserted.
The EPC1LC20's 20-pin PLCC package has no exposed thermal pad and dissipates negligible power (typical 50 mW active, 10 mW standby). Standard FR-4 PCB thermal design is sufficient; no heatsink required. However, in enclosed industrial enclosures with ambient temperatures above 70°C, verify that the IC junction temperature stays below the maximum rating by improving airflow or derating adjacent components.
コンプライアンス情報
Compliance status not present in Verified Web Data; per the obsolete lifecycle flag, the part may predate RoHS transition. Use lead-free variant or EPCQ-series for new RoHS-compliant designs.
