EPC2CC20N - Altera PLCC-20 SRAM Configurator | FPGA
部品番号: EPC2CC20N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
EPC2CC20N 概要
A configuration device is a non-volatile memory IC whose role in a digital system is to store the FPGA's configuration bitstream and load it into the SRAM cells of the FPGA at power-up or reconfiguration. Because SRAM-based LUT FPGAs lose their configuration when power is removed, a configuration device is mandatory for any standalone (non-JTAG) boot. The EPC2 family sits in the hierarchy: configuration device -> non-volatile memory -> memory IC -> programmable logic support. The EPC2CC20N specifically targets mid-density Altera LUT families such as ACEX, APEX, Cyclone, and similar devices that use a 16-bit parallel configuration bus.
Key features of the EPC2CC20N include a 3.3V single-supply operation, JTAG-compliant in-system programmability via IEEE 1149.1 boundary scan, and built-in error detection through a 16-bit CRC on each configuration frame. The device supports both FPP (Fast Passive Parallel) and PS (Passive Serial) configuration modes when paired with the appropriate Altera FPGA, and exposes a CONF_DONE/open-drain status pin for handshaking with the system controller. Programming is performed through the standard Altera ByteBlasterMV or USB-Blaster download cable.
From an architectural standpoint, the EPC2CC20N integrates the configuration bitstream array, JTAG controller, address generation logic, parallel data output drivers, and a dedicated configuration controller block that sequences the load process to the FPGA. The internal oscillator and timing generation remove the need for an external clock during configuration. Multiple EPC2 devices can also be cascaded to configure larger FPGAs whose bitstream exceeds a single device's capacity.
Typical applications include factory programming of Altera ACEX 1K, APEX 20K, Cyclone, and MAX 7000/3000A support boards, industrial control systems using mid-density FPGAs, and prototyping platforms where a non-volatile boot source is required. The PLCC-20 through-hole package supports robust production sockets and field-replaceable modules.
When designing with the EPC2CC20N, confirm that the target FPGA's configuration mode (FPP/PS) and data width match the EPC2's interface. Add a 0.1uF decoupling capacitor close to VCC, and follow Altera's recommended pull-ups on nSTATUS and CONF_DONE lines. Designers migrating to newer Altera/Intel devices should consider the EPCQ-series serial configurators for new designs, as the EPC2 is a legacy family.
This page synthesizes distributor stock signals, same-family Altera alternatives such as EPC2C20 and EPC22C20N, and practical design notes not found in a single distributor listing. Compared to a bare product page, it provides drop-in cross-reference, pricing tiers, and application-specific guidance.
ドロップイン代替品: EPC2CC20N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC2CC20N （同一形状・フットプリント） — 相違点: Mounting Type, Configuration Interface, Package, Memory Type, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPC2C20
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPC22C20N
✅ ドロップイン✓ 在庫あり
$11.4 / 個
データシートを見る →EPC22LC20
✅ ドロップイン✓ 在庫あり
$4.1 / 個
データシートを見る →EPC21LC20
✅ ドロップイン✓ 在庫あり
$10.4 / 個
データシートを見る →EPC1LC20
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EPC2C20N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPC22C20N
✅ ドロップイン✓ 在庫あり
$11.4 / 個
データシートを見る →EPC2CC20N 最大定格＆電気的特性
| 機能 | Configuration device for SRAM-based LUT FPGAs |
| パッケージ | PLCC-20 |
| Configuration Interface | 16-bit parallel (FPP) / Passive Serial (PS) |
| Supply Voltage (VCC) | 3.3 V |
| Programming Interface | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| In-System Programmable | Yes |
| Error Detection | 16-bit CRC on configuration frames |
| Configuration Modes Supported | FPP and PS (depends on host FPGA) |
| Cascadable | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | Yes (CONF_DONE / nSTATUS compatible) |
| 実装タイプ | Surface Mount (PLCC-20 socket compatible) |
EPC2CC20N ピン構成
| ピン 1 | DATA0 — Configuration data bit 0 |
| ピン 2 | DATA1 — Configuration data bit 1 |
| ピン 3 | DATA2 — Configuration data bit 2 |
| ピン 4 | DATA3 — Configuration data bit 3 |
| ピン 5 | DATA4 — Configuration data bit 4 |
| ピン 6 | DATA5 — Configuration data bit 5 |
| ピン 7 | DATA6 — Configuration data bit 6 |
| ピン 8 | DATA7 — Configuration data bit 7 |
| ピン 9 | GND — Ground |
| ピン 10 | DATA8 — Configuration data bit 8 |
| ピン 11 | DATA9 — Configuration data bit 9 |
| ピン 12 | DATA10 — Configuration data bit 10 |
| ピン 13 | DATA11 — Configuration data bit 11 |
| ピン 14 | DATA12 — Configuration data bit 12 |
| ピン 15 | DATA13 — Configuration data bit 13 |
| ピン 16 | DATA14 — Configuration data bit 14 |
| ピン 17 | DATA15 — Configuration data bit 15 |
| ピン 18 | nSTATUS / CONF_DONE — Open-drain configuration status (refer to datasheet for mode) |
| ピン 19 | VCC — 3.3V supply |
| ピン 20 | JTAG / nCS — JTAG or chip-select (refer to datasheet for mode) |
主な用途
EPC2CC20N の用途: 7 件s: ACEX 1K FPGA Configuration Storage, APEX 20K Boot Source, Cyclone I/II/III Legacy Board Support, MAX 7000A / 3000A Configuration Backup, Industrial PLC FPGA Subsystem, Factory Pre-Programming Socket, Military / Aerospace Legacy Support.
ACEX 1K FPGA Configuration Storage
The EPC2CC20N is the reference Altera configuration device for ACEX 1K (EP1K) FPGAs in industrial and legacy designs, providing non-volatile bitstream storage for densities up to the EPC2 family limit. The 16-bit parallel data bus and FPP mode match the ACEX 1K's configuration controller, enabling fast boot times under 100 ms with the EPC2CC20N's internal oscillator driving the configuration clock. Engineers should confirm CONF_DONE pull-up and nSTATUS open-drain wiring per ACEX 1K handbook reference designs. The PLCC-20 socket allows factory programming via JTAG then field installation without socketed rework.
おすすめ
APEX 20K Boot Source
The EPC2CC20N serves as the boot configuration source for Altera APEX 20K (EP20K) multi-core FPGAs in telecom and DSP applications. The FPP 16-bit interface and CONF_DONE handshaking match APEX 20K's configuration controller, supporting bitstream densities up to the EPC2 family limit. For APEX 20K parts with bitstreams exceeding single-device capacity, multiple EPC2CC20N units can be cascaded by tying nCS and CONF_DONE in a daisy-chain. Industrial temperature grade and PLCC-20 socket compatibility make the EPC2CC20N ideal for outdoor telecom line cards where factory pre-programming is desired.
おすすめ
Cyclone I/II/III Legacy Board Support
Legacy Cyclone FPGA designs that use parallel configuration can be supported by the EPC2CC20N through Altera's FPP mode. Although newer Cyclone devices prefer active serial (AS) configuration with EPCQ devices, original Cyclone I (EP1C) and Cyclone II (EP2C) reference designs used the EPC2CC20N. Engineers maintaining legacy Cyclone boards benefit from the PLCC-20 socket that allows field replacement without PCB rework. Migrating to AS-mode EPCQ16 is recommended for new designs, but the EPC2CC20N remains a valid support part for the installed base through 2026.
おすすめ
MAX 7000A / 3000A Configuration Backup
Although MAX 7000A CPLDs are non-volatile and do not strictly require a configuration device, the EPC2CC20N is sometimes deployed as a remote-update bitstream storage when MAX 7000A designs are paired with an FPGA. The PLCC-20 socket simplifies factory programming flow, and the 3.3V supply matches MAX 7000A's VCCIO. For new designs, designers should confirm whether the host CPLD actually requires a configuration device - many MAX 7000A applications are self-sufficient and the EPC2CC20N would be optional. Industrial temp grade suits factory floor deployment.
おすすめ
Industrial PLC FPGA Subsystem
The EPC2CC20N is deployed in industrial PLC and process control designs that integrate mid-density Altera FPGAs for custom I/O and protocol bridging. The 3.3V supply aligns with PLC backplane rails, and the PLCC-20 package supports field-replaceable modules - critical for plants where downtime must be minimized. JTAG in-system programmability allows firmware updates via Altera's USB-Blaster without removing the EPC2CC20N from its socket. The cascadable architecture supports large bitstreams when the PLC's FPGA is a high-density ACEX or APEX part. Operating temperature grade supports -40C to +85C industrial environments.
おすすめ
Factory Pre-Programming Socket
The EPC2CC20N's PLCC-20 package is widely used as a factory pre-programming socket where the bitstream is loaded via JTAG before the device is socketed onto the production board. This flow separates FPGA configuration storage from the main PCB assembly, simplifying field upgrades and rework. Programming is performed via Altera's ByteBlasterMV or USB-Blaster cable using Quartus Prime Programmer. The PLCC-20 socket also enables secure manufacturing flows where bitstream IP is loaded in a controlled environment rather than at the production line.
おすすめ
Military / Aerospace Legacy Support
Long-lifecycle military and aerospace programs that standardized on ACEX 1K and APEX 20K FPGAs continue to deploy the EPC2CC20N for configuration storage. The PLCC-20 package's mechanical robustness suits avionics and shipboard platforms, and Altera's controlled manufacturing baseline supports long-term program continuity. Designers should verify the exact temperature grade and QML qualification status with the manufacturer, as NRND lifecycle status may affect long-term availability. For new military programs, the Microsemi (Microchip) equivalent AX-series configurators or Intel's radiation-tolerant offerings may be preferred.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC2CC20N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC2C20 | EPC22C20N | EPC22LC20 | EPC21LC20 | EPC1LC20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-20 | PLCC-20 (same) | PLCC-20 (same) | PLCC-20 (same) | PLCC-20 (same) | PLCC-20 (same) |
| Supply Voltage | 3.3 V | 3.3 V | 5 V | 5 V | 5 V | 5 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | No | No | No | No |
| CRC Error Detection | 16-bit | 16-bit | No | No | No | No |
| Configuration Mode | FPP / PS | FPP / PS | PS only | PS only | PS only | PS only |
| Family | EPC2 (Enhanced 3.3V) | EPC2 (Enhanced 3.3V) | EPC2 (Legacy 5V) | EPC2 (Legacy 5V Low-Power) | EPC1 (Legacy 5V) | EPC1 (Legacy 5V) |
| Lifecycle Status | NRND | NRND | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Enhanced 3.3V configuration device with JTAG ISP and 16-bit CRC （vs EPC22C20N)
- FPP and PS configuration mode support （vs EPC21LC20)
- Cascadable for larger bitstreams （vs EPC1LC20)
設計ノート
Estimated: at 3.3V supply and typical configuration active current of approximately 50 mA, the EPC2CC20N dissipates roughly 165 mW during configuration. Decouple VCC (pin 19) with a 0.1uF ceramic capacitor placed within 3 mm of the pin to suppress switching transients when the FPGA begins to draw configuration data. A bulk 10uF tantalum or ceramic capacitor on the same rail further reduces supply droop during cascaded multi-device configuration. Add a ferrite bead if the same 3.3V rail also feeds a switching regulator that could couple noise into the configuration clock path.
Estimated: route the 16-bit parallel data bus (DATA[15:0]) with matched lengths (within 5 mm) to avoid configuration skew on the host FPGA. Place the EPC2CC20N within 50 mm of the FPGA's configuration data pins to minimize signal integrity issues at high FPP clock rates. Keep the JTAG chain (TCK/TMS/TDO/TDI) isolated from switching power traces; route TDI/TDO as a differential pair if chain length exceeds 25 mm. Place CONF_DONE and nSTATUS pull-ups (typically 4.7 kohm to VCC) close to the EPC2CC20N, not the FPGA, to avoid glitches during power-up.
Common pitfalls when designing with the EPC2CC20N: (1) Forgetting the nSTATUS and CONF_DONE pull-up resistors - without them the host FPGA will not detect configuration completion and remain in reset. (2) Mixing 5V EPC22LC20/EPC1LC20 with the 3.3V EPC2CC20N - VCC rails are NOT interchangeable and will damage the part or cause read errors. (3) Programming via JTAG without first setting the Quartus Prime device list to EPC2 - wrong device selection will corrupt the bitstream. (4) For legacy designs, do not assume new EPC2CC20N date codes are bitstream-compatible with old ACEX 1K bitstreams - verify in Quartus Prime before production.
コンプライアンス情報
RoHS/REACH compliance not explicitly confirmed in verified data; EPC2 family is a legacy Altera product line predating full RoHS transition. AEC-Q100 is not applicable - this is a configuration memory device, not an automotive-qualified IC. Conflict minerals compliance follows Altera (now Intel) standard policy.
