EPF10K10ATC144-3N - FLEX 10KA FPGA 10K Gates 576 Cells | Intel
部品番号: EPF10K10ATC144-3N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $42.91 | $42.91 |
| 10 | $39.2 | $392.00 |
| 100 | $33.85 | $3,385.00 |
| 500 | $28.4 | $14,200.00 |
| 1,000 | $24.75 | $24,750.00 |
EPF10K10ATC144-3N 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit that can be configured by the customer after manufacture to implement arbitrary digital logic. FPGAs sit within the broader taxonomy of programmable logic devices (PLDs), alongside CPLDs and SPLDs, and historically bridged the gap between fixed-function ASICs and discrete logic. The FLEX 10KA family occupies a unique position in PLD history as one of the first families to embed memory blocks inside the fabric, eliminating the need for separate SRAM chips for FIFO and small memory structures.
Key features of the EPF10K10ATC144-3N include 72 Logic Array Blocks (LABs), 576 logic elements, an embedded array of EABs, and 102 maximum user I/Os. The device supports in-system programmability via an IEEE 1149.1 (JTAG) interface and is supported by the legacy Altera MAX+PLUS II and Quartus design toolchains. With a maximum toggle frequency around 125 MHz in the -3 speed grade, the part targets glue-logic, bus-bridging, and low-density state-machine applications rather than high-performance signal processing.
Architecturally, FLEX 10KA devices integrate a four-input LUT-based logic fabric with rows of embedded array blocks (EABs) that can each implement up to 2 Kbits of dual-port RAM or ROM. The routing interconnect uses continuous FastTrack channels, providing predictable timing that historically simplified design closure compared to segmented routing. The -3 speed grade corresponds to a faster propagation delay than the -2 and -1 grades, making the -3N variant the highest-performance member of the FLEX 10K10A family.
Typical applications for the EPF10K10ATC144-3N include legacy telecom interface cards, industrial PLC glue logic, prototyping platforms, motor-control state machines, and embedded control bridges. The 144-pin TQFP package supports hand-soldering and rework, which is valuable for low-volume legacy systems and field upgrades.
When designing with this part, engineers should verify MAX+PLUS II or Quartus tool support because this family is mature and tool compatibility matters for long-term maintenance. The 3.3 V supply requirement and 0 °C to 70 °C commercial temperature window should be checked against the target environment; the EPF10K10ATI144-3N industrial-grade variant is required for extended temperature operation.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. All specifications are sourced from the Intel/Altera FLEX 10KA datasheet and current distributor listings as of 2026-09-11.
ドロップイン代替品: EPF10K10ATC144-3N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPF10K10ATC144-3N （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Speed Grade, Process Technology, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EPF10K10ATC144-3
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPF10K10ATC144-2
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EPF10K10ATC144-1N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPF10K10ATI144-3N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPF10K10ATI144-3
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPF10K10ATC144-3N 最大定格＆電気的特性
| Family | FLEX 10KA |
| Series | FLEX-10KA® |
| Typical Gates | 10,000 gates |
| Logic Cells / Elements | 576 cells |
| Number of LABs | 72 |
| Maximum User I/Os | 102 |
| Process Technology | 0.3 µm CMOS |
| Core Supply Voltage | 3.3 V |
| Maximum Toggle Frequency | 125 MHz |
| Propagation Delay | 0.6 ns (per digchip listing) |
| 動作温度 | 0 °C to 70 °C (commercial) |
| パッケージ | 144-pin TQFP (LQFP, 144-LQFP) |
| 実装タイプ | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster |
| Embedded Memory | Embedded Array Blocks (EABs), up to 2 Kbit each |
| RoHS ステータス | Non-Compliant (lead-bearing N suffix variant) |
| Lead-Free Status | Contains lead (per FindIC) |
EPF10K10ATC144-3N ピン構成
| ピン 1 | I/O — User I/O pin (varies by bank; see datasheet pin table) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | VCCINT — Core supply voltage (3.3 V) |
| ピン 6 | GND — Ground |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | TDI — JTAG Test Data In |
| ピン 15 | TMS — JTAG Test Mode Select |
| ピン 16 | TCK — JTAG Test Clock |
| ピン 17 | nSTATUS — Configuration status (open-drain) |
| ピン 18 | nCONFIG — Configuration control (active-low) |
| ピン 19 | CONF_DONE — Configuration done (open-drain) |
| ピン 20 | DCLK — Configuration clock input |
| ピン 21 | DATA0 — Configuration data input |
| ピン 22 | nCE — Chip enable (active-low) |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | I/O — User I/O pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | VCCIO — I/O supply voltage |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | I/O — User I/O pin |
| ピン 42 | I/O — User I/O pin |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | GND — Ground |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | VCCINT — Core supply voltage (3.3 V) |
| ピン 56 | GND — Ground |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | VCCIO — I/O supply voltage |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | I/O — User I/O pin |
| ピン 85 | I/O — User I/O pin |
| ピン 86 | VCCINT — Core supply voltage (3.3 V) |
| ピン 87 | I/O — User I/O pin |
| ピン 88 | I/O — User I/O pin |
| ピン 89 | I/O — User I/O pin |
| ピン 90 | GND — Ground |
| ピン 91 | I/O — User I/O pin |
| ピン 92 | I/O — User I/O pin |
| ピン 93 | I/O — User I/O pin |
| ピン 94 | I/O — User I/O pin |
| ピン 95 | I/O — User I/O pin |
| ピン 96 | I/O — User I/O pin |
| ピン 97 | I/O — User I/O pin |
| ピン 98 | I/O — User I/O pin |
| ピン 99 | I/O — User I/O pin |
| ピン 100 | I/O — User I/O pin |
| ピン 101 | I/O — User I/O pin |
| ピン 102 | I/O — User I/O pin |
| ピン 103 | GND — Ground |
| ピン 104 | I/O — User I/O pin |
| ピン 105 | I/O — User I/O pin |
| ピン 106 | I/O — User I/O pin |
| ピン 107 | I/O — User I/O pin |
| ピン 108 | I/O — User I/O pin |
| ピン 109 | VCCIO — I/O supply voltage |
| ピン 110 | I/O — User I/O pin |
| ピン 111 | I/O — User I/O pin |
| ピン 112 | I/O — User I/O pin |
| ピン 113 | I/O — User I/O pin |
| ピン 114 | I/O — User I/O pin |
| ピン 115 | I/O — User I/O pin |
| ピン 116 | I/O — User I/O pin |
| ピン 117 | I/O — User I/O pin |
| ピン 118 | I/O — User I/O pin |
| ピン 119 | I/O — User I/O pin |
| ピン 120 | GND — Ground |
| ピン 121 | I/O — User I/O pin |
| ピン 122 | I/O — User I/O pin |
| ピン 123 | I/O — User I/O pin |
| ピン 124 | I/O — User I/O pin |
| ピン 125 | I/O — User I/O pin |
| ピン 126 | I/O — User I/O pin |
| ピン 127 | I/O — User I/O pin |
| ピン 128 | I/O — User I/O pin |
| ピン 129 | I/O — User I/O pin |
| ピン 130 | I/O — User I/O pin |
| ピン 131 | I/O — User I/O pin |
| ピン 132 | VCCINT — Core supply voltage (3.3 V) |
| ピン 133 | GND — Ground |
| ピン 134 | I/O — User I/O pin |
| ピン 135 | I/O — User I/O pin |
| ピン 136 | I/O — User I/O pin |
| ピン 137 | I/O — User I/O pin |
| ピン 138 | I/O — User I/O pin |
| ピン 139 | TDO — JTAG Test Data Out |
| ピン 140 | I/O — User I/O pin |
| ピン 141 | I/O — User I/O pin |
| ピン 142 | I/O — User I/O pin |
| ピン 143 | I/O — User I/O pin |
| ピン 144 | I/O — User I/O pin |
主な用途
EPF10K10ATC144-3N の用途: 6 件s: Legacy Telecom Interface Cards, Industrial PLC Glue Logic, Motor Control State Machines, Embedded Control Bridges, Prototyping and Education Platforms, Legacy Bus Interface Cards.
Legacy Telecom Interface Cards
The EPF10K10ATC144-3N is well-suited to legacy telecom interface cards where 10,000 gates, 102 user I/Os, and a 125 MHz toggle frequency are sufficient for protocol bridging, framing, and clock-recovery glue logic. With 3.3 V core supply and 0.6 ns propagation delay, the device handles E1/T1 framer interconnects and HDLC-style state machines. Its embedded array blocks (EABs) can implement small FIFOs and lookup tables, eliminating external SRAM. The 144-pin TQFP supports hand rework that legacy telecom field-service technicians rely on. Compiled with MAX+PLUS II, the design files remain portable to Quartus for ongoing maintenance.
おすすめ
Industrial PLC Glue Logic
For industrial PLC backplanes and field-bus bridges, the EPF10K10ATC144-3N delivers the gate density needed to consolidate discrete 74-series logic, custom state machines, and bus-arbitration circuits onto a single programmable device. Its 576 logic elements arranged in 72 LABs are well-matched to ladder-logic migration and IEC 61131-style sequencer designs. The 102 user I/Os accommodate multiple field-bus interfaces (Profibus, Modbus) plus local GPIO. Embedded array blocks can host lookup tables for PID coefficients and small CAM tables. Note that the commercial 0 °C to 70 °C temperature grade requires the industrial EPF10K10ATI144-3N for cabinet-mounted applications.
おすすめ
Motor Control State Machines
The EPF10K10ATC144-3N's 125 MHz performance and embedded memory make it a strong fit for brushless DC and stepper motor control state machines that demand deterministic timing and small lookup tables. The 72 LABs can encode commutation tables, ramp generators, and PWM modulator logic; EABs host sine-drive and space-vector modulation coefficients. With 102 user I/Os, the FPGA can directly interface Hall sensors, quadrature encoders, and FET gate drivers without external bus expanders. The -3 speed grade's 0.6 ns propagation delay supports high-resolution PWM at low duty cycle. Hardware engineers migrating to MAX 10 should evaluate 10M02SCE144I7G with similar gate count.
おすすめ
Embedded Control Bridges
The EPF10K10ATC144-3N serves as an embedded control bridge between mismatched processors, memory, and peripheral buses. With 10K gates and 102 user I/Os, it can host I2C/SPI to parallel-bus bridges, UART multiplexers, and address-decoding glue logic. The 576 logic cells support full 8/16-bit datapath implementations and small FIFO buffers using EAB blocks. JTAG programming (IEEE 1149.1) allows in-system reprogramming during development and field updates, critical for control-bridge designs that must adapt to multiple product variants. The 144-pin TQFP footprint simplifies PCB layout for bridges placed between BGA processors and through-hole legacy peripherals.
おすすめ
Prototyping and Education Platforms
Universities and engineering labs rely on the EPF10K10ATC144-3N as a teaching vehicle for programmable-logic courses and digital-design prototyping. Its manageable 10K-gate density lets students implement complete RISC-like CPUs, UART controllers, and VGA generators within a single semester. The MAX+PLUS II and Quartus toolchains are mature and well-documented, with abundant example projects and reference designs freely available. The 144-pin TQFP package on 0.5 mm pitch is large enough for educational soldering but small enough to fit on a student project board. EAB blocks teach the concept of distributed on-chip memory, a foundational concept for modern FPGA education.
おすすめ
Legacy Bus Interface Cards
The EPF10K10ATC144-3N is a proven solution for legacy VMEbus, ISA, and PCI-style interface cards where existing designs must remain operational without requalification. Its 102 user I/Os comfortably drive 32-bit address/data buses plus control signals, and the embedded EABs implement bus-master FIFOs and address-mapping registers. The -3 speed grade's 125 MHz toggle frequency supports PCI 33 MHz bus timing with adequate margin. Industrial and defense customers value the long-term stability of the FLEX 10KA silicon, which has been in production since the late 1990s. Migration paths to MAX II or MAX 10 require PCB rework but preserve the design's Verilog/VHDL source.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPF10K10ATC144-3N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPF10K10ATC144-3 | EPF10K10ATC144-2 | EPF10K10ATC144-1N | EPF10K10ATI144-3N | EPF10K10ATI144-3 |
|---|---|---|---|---|---|---|
| Package | 144-pin TQFP (LQFP) | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Speed Grade | -3 (fastest) | -3 (same as target) | -2 (slower, ~100 MHz) | -1 (slowest grade) | -3 (same speed grade) | -3 (same speed grade) |
| Operating Temperature | 0 °C to 70 °C (commercial) | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) |
| Logic Cells | 576 | 576 | 576 | 576 | 576 | 576 |
| Number of LABs | 72 | 72 | 72 | 72 | 72 | 72 |
| User I/Os | 102 | 102 | 102 | 102 | 102 | 102 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| RoHS Status | Non-Compliant (lead-bearing) | Non-Compliant (lead-bearing) | Non-Compliant (lead-bearing) | Non-Compliant (lead-bearing) | Non-Compliant (lead-bearing) | Non-Compliant (lead-bearing) |
主な差別化要因
- Highest speed grade in FLEX 10K10A TQFP-144 family （vs EPF10K10ATC144-2)
- Commercial temperature, lead-bearing package available for legacy customers （vs EPF10K10ATI144-3N)
- Lower pin count than 208-pin PQFP alternative but same die （vs EPF10K10AQC208-3N)
設計ノート
The EPF10K10ATC144-3N requires a stable 3.3 V VCCINT supply with bulk decoupling of at least 100 µF tantalum plus 0.1 µF ceramic per VCCINT pin pair. Because this part is obsolete and may have variable I/O bank (VCCIO) tolerance, measure VCCIO before connecting to 5 V peripherals; FLEX 10KA I/O is not 5 V-tolerant in most bank configurations, so external level shifters are required for 5 V bus interfaces. Power-on ramp should follow the FLEX 10KA datasheet sequencing to avoid inadvertent configuration mode entry.
The EPF10K10ATC144-3N is lead-bearing and non-RoHS-compliant, which causes regulatory issues for new products entering the EU market. Engineers should verify the device family revision: only the -3N suffix means 3.3 V commercial lead-free variant; older -3 (without N) are lead-bearing. JTAG chain ordering with other 1149.1 devices on the board must keep TDI/TDO paths short because the EPF10K10ATC144-3N does not include a JTAG bypass register chain isolation - use BSDL files to validate the chain during bring-up.
The 144-pin TQFP at 0.5 mm pitch requires careful PCB land pattern design with solder mask-defined (SMD) pads to prevent tombstoning during reflow. Place decoupling capacitors as close as possible to each VCCINT/VCCIO pin pair, and route GND on an internal ground plane directly under the device for thermal dissipation and signal return paths. Configuration-related pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) need pull-up resistors per datasheet; leave room on the PCB for the ByteBlaster JTAG header for in-system reprogramming during development.
Estimated: at typical 3.3 V supply and 100 MHz operation with all 576 logic cells active (worst-case utilization), the EPF10K10ATC144-3N consumes approximately 250-400 mW. With the 144-pin TQFP thermal resistance around 35 °C/W on a JEDEC 2s2p test board, junction temperature rise is approximately 9-14 °C above ambient. Commercial 0-70 °C range is rarely challenged in normal operation, but designers should still provide modest copper pour thermal relief on VCCINT and GND pads to keep Tj below the 85 °C recommended long-term limit.
コンプライアンス情報
Per FindIC compare data, the EPF10K10ATC144-3N is flagged 'Non-Compliant' for RoHS and 'Contains Lead' for lead-free status. The N suffix historically indicated lead-bearing variant. REACH, halogen-free, and conflict-minerals status not explicitly stated in available data; flagged as unknown.
