EPF8820ARI208-2 - FLEX 8000 FPGA, 672 Logic Elements | Altera
部品番号: EPF8820ARI208-2 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.8 | $6,400.00 |
| 1,000 | $11.5 | $11,500.00 |
EPF8820ARI208-2 概要
An FPGA (Field Programmable Gate Array) is a reprogrammable semiconductor device whose logic function is defined by configuration bitstream rather than fixed metal mask. FPGAs sit at the top of the programmable logic hierarchy: programmable logic device (PLD) -> complex PLD (CPLD) -> FPGA. SRAM-based FPGAs such as the FLEX 8000 family are volatile and must be reconfigured at every power-up from an external memory (EPROM) or Altera serial configuration device (EPC1, EPC1213, EPC1064, EPC1441).
Key features of the EPF8820ARI208-2 include 672 logic elements, 152 maximum user I/O pins, 6 embedded array blocks (EABs) of 2 Kbits each, in-system reprogrammability via JTAG, and a typical gate count of 8,000 usable gates. The -2 speed grade indicates a moderate-speed bin of the silicon, suitable for cost-sensitive commercial designs. The device supports multiple I/O standards including TTL and CMOS, allowing flexible interfacing to legacy and modern logic families.
The FLEX 8000 architecture uses a four-input LUT per logic element with a dedicated register, providing predictable timing and a register-to-logic ratio well-suited for pipelined datapaths. The FastTrack continuous routing fabric and row/column interconnect provide predictable delays independent of placement, simplifying static timing closure in mid-complexity designs.
Typical applications include industrial control logic, telecommunications interface glue, prototyping platforms for ASIC emulation, and educational hardware design. The wide I/O count (152 user pins) allows direct connection to parallel buses, memory interfaces, and multiple peripheral buses without external bus expander logic. The SRAM configuration also enables rapid design iteration via JTAG or EPC device reprogramming.
When designing with the EPF8820ARI208-2, ensure an external configuration memory is selected because the SRAM configuration is volatile. The 208-pin package provides ample I/O but requires a 4-layer PCB with controlled-impedance traces for stable operation above 50 MHz. JTAG programming via the Altera ByteBlaster or compatible download cable is the standard development flow.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a one-stop engineering reference for sourcing and integrating this legacy FLEX 8000 FPGA.
ドロップイン代替品: EPF8820ARI208-2 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPF8820ARI208-2 （同一形状・フットプリント） — 相違点: Package, Process Technology, Configuration Method, Usable Gates, Speed Grade.
クイック比較ツール — 並列比較する代替部品を選択:
EPF8820ARC208-2
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPF8820ARC208-2N
✅ ドロップイン✓ 在庫あり
$20.55 / 個
データシートを見る →EPF8820ARI208-1
✅ ドロップイン✓ 在庫あり
$20.4 / 個
データシートを見る →EPF8820ARC208-3
✅ ドロップイン✓ 在庫あり
$62 / 個
データシートを見る →EPF8820ARC208-4
✅ ドロップイン✓ 在庫あり
$25.4 / 個
データシートを見る →EPF8820ARC208-5
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPF8820ARI208-2 最大定格＆電気的特性
| Family | FLEX 8000 |
| Logic Elements | 672 |
| Maximum User I/O | 152 |
| Embedded Array Blocks (EABs) | 6 |
| Total Embedded Memory | 16 Kbits (approximately) |
| Usable Gates | 8,000 (typical) |
| Configuration Technology | SRAM (volatile) |
| Speed Grade | -2 |
| パッケージ | 208-pin RQFP (RFI) |
| Operating Voltage (VCCINT) | 5 V |
| Programming Interface | JTAG (IEEE 1149.1) / Altera ByteBlaster |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +70C (commercial) |
| Configuration Devices Supported | EPC1, EPC1213, EPC1064, EPC1441 |
| RoHS ステータス | Compliant (per DigiKey listing) |
EPF8820ARI208-2 ピン構成
| ピン 1 | I/O — User I/O pin (bank 1) |
| ピン 2 | I/O — User I/O pin (bank 1) |
| ピン 3 | I/O — User I/O pin (bank 1) |
| ピン 4 | I/O — User I/O pin (bank 1) |
| ピン 5 | I/O — User I/O pin (bank 1) |
| ピン 6 | I/O — User I/O pin (bank 1) |
| ピン 7 | I/O — User I/O pin (bank 1) |
| ピン 8 | VCCINT — Core logic supply (5V) |
| ピン 9 | I/O — User I/O pin (bank 1) |
| ピン 10 | I/O — User I/O pin (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (bank 2) |
| ピン 13 | I/O — User I/O pin (bank 2) |
| ピン 14 | I/O — User I/O pin (bank 2) |
| ピン 15 | I/O — User I/O pin (bank 2) |
| ピン 16 | I/O — User I/O pin (bank 2) |
| ピン 17 | I/O — User I/O pin (bank 2) |
| ピン 18 | I/O — User I/O pin (bank 2) |
| ピン 19 | VCCIO — I/O supply voltage |
| ピン 20 | I/O — User I/O pin (bank 2) |
| ピン 21 | I/O — User I/O pin (bank 2) |
| ピン 22 | GND — Ground |
| ピン 23 | I/O — User I/O pin (bank 3) |
| ピン 24 | I/O — User I/O pin (bank 3) |
| ピン 25 | I/O — User I/O pin (bank 3) |
| ピン 26 | I/O — User I/O pin (bank 3) |
| ピン 27 | I/O — User I/O pin (bank 3) |
| ピン 28 | I/O — User I/O pin (bank 3) |
| ピン 29 | I/O — User I/O pin (bank 3) |
| ピン 30 | VCCINT — Core logic supply (5V) |
| ピン 31 | I/O — User I/O pin (bank 3) |
| ピン 32 | I/O — User I/O pin (bank 3) |
| ピン 33 | GND — Ground |
| ピン 34 | I/O — User I/O pin (bank 4) |
| ピン 35 | I/O — User I/O pin (bank 4) |
| ピン 36 | I/O — User I/O pin (bank 4) |
| ピン 37 | I/O — User I/O pin (bank 4) |
| ピン 38 | I/O — User I/O pin (bank 4) |
| ピン 39 | I/O — User I/O pin (bank 4) |
| ピン 40 | I/O — User I/O pin (bank 4) |
| ピン 41 | VCCIO — I/O supply voltage |
| ピン 42 | I/O — User I/O pin (bank 4) |
| ピン 43 | I/O — User I/O pin (bank 4) |
| ピン 44 | GND — Ground |
| ピン 45 | I/O — User I/O pin (bank 5) |
| ピン 46 | I/O — User I/O pin (bank 5) |
| ピン 47 | I/O — User I/O pin (bank 5) |
| ピン 48 | I/O — User I/O pin (bank 5) |
| ピン 49 | I/O — User I/O pin (bank 5) |
| ピン 50 | I/O — User I/O pin (bank 5) |
| ピン 51 | I/O — User I/O pin (bank 5) |
| ピン 52 | VCCINT — Core logic supply (5V) |
| ピン 53 | I/O — User I/O pin (bank 5) |
| ピン 54 | I/O — User I/O pin (bank 5) |
| ピン 55 | GND — Ground |
| ピン 56 | I/O — User I/O pin (bank 6) |
| ピン 57 | I/O — User I/O pin (bank 6) |
| ピン 58 | I/O — User I/O pin (bank 6) |
| ピン 59 | I/O — User I/O pin (bank 6) |
| ピン 60 | I/O — User I/O pin (bank 6) |
| ピン 61 | I/O — User I/O pin (bank 6) |
| ピン 62 | I/O — User I/O pin (bank 6) |
| ピン 63 | VCCIO — I/O supply voltage |
| ピン 64 | I/O — User I/O pin (bank 6) |
| ピン 65 | I/O — User I/O pin (bank 6) |
| ピン 66 | GND — Ground |
| ピン 67 | I/O — User I/O pin (bank 7) |
| ピン 68 | I/O — User I/O pin (bank 7) |
| ピン 69 | I/O — User I/O pin (bank 7) |
| ピン 70 | I/O — User I/O pin (bank 7) |
| ピン 71 | I/O — User I/O pin (bank 7) |
| ピン 72 | I/O — User I/O pin (bank 7) |
| ピン 73 | I/O — User I/O pin (bank 7) |
| ピン 74 | VCCINT — Core logic supply (5V) |
| ピン 75 | I/O — User I/O pin (bank 7) |
| ピン 76 | I/O — User I/O pin (bank 7) |
| ピン 77 | GND — Ground |
| ピン 78 | I/O — User I/O pin (bank 8) |
| ピン 79 | I/O — User I/O pin (bank 8) |
| ピン 80 | I/O — User I/O pin (bank 8) |
| ピン 81 | I/O — User I/O pin (bank 8) |
| ピン 82 | I/O — User I/O pin (bank 8) |
| ピン 83 | I/O — User I/O pin (bank 8) |
| ピン 84 | I/O — User I/O pin (bank 8) |
| ピン 85 | VCCIO — I/O supply voltage |
| ピン 86 | I/O — User I/O pin (bank 8) |
| ピン 87 | I/O — User I/O pin (bank 8) |
| ピン 88 | GND — Ground |
| ピン 89 | I/O — User I/O pin (bank 1) |
| ピン 90 | I/O — User I/O pin (bank 1) |
| ピン 91 | I/O — User I/O pin (bank 1) |
| ピン 92 | I/O — User I/O pin (bank 1) |
| ピン 93 | I/O — User I/O pin (bank 1) |
| ピン 94 | I/O — User I/O pin (bank 1) |
| ピン 95 | I/O — User I/O pin (bank 1) |
| ピン 96 | VCCINT — Core logic supply (5V) |
| ピン 97 | I/O — User I/O pin (bank 1) |
| ピン 98 | I/O — User I/O pin (bank 1) |
| ピン 99 | GND — Ground |
| ピン 100 | I/O — User I/O pin (bank 2) |
| ピン 101 | I/O — User I/O pin (bank 2) |
| ピン 102 | I/O — User I/O pin (bank 2) |
| ピン 103 | I/O — User I/O pin (bank 2) |
| ピン 104 | I/O — User I/O pin (bank 2) |
| ピン 105 | I/O — User I/O pin (bank 2) |
| ピン 106 | I/O — User I/O pin (bank 2) |
| ピン 107 | VCCIO — I/O supply voltage |
| ピン 108 | I/O — User I/O pin (bank 2) |
| ピン 109 | I/O — User I/O pin (bank 2) |
| ピン 110 | GND — Ground |
| ピン 111 | I/O — User I/O pin (bank 3) |
| ピン 112 | I/O — User I/O pin (bank 3) |
| ピン 113 | I/O — User I/O pin (bank 3) |
| ピン 114 | I/O — User I/O pin (bank 3) |
| ピン 115 | I/O — User I/O pin (bank 3) |
| ピン 116 | I/O — User I/O pin (bank 3) |
| ピン 117 | I/O — User I/O pin (bank 3) |
| ピン 118 | VCCINT — Core logic supply (5V) |
| ピン 119 | I/O — User I/O pin (bank 3) |
| ピン 120 | I/O — User I/O pin (bank 3) |
| ピン 121 | GND — Ground |
| ピン 122 | I/O — User I/O pin (bank 4) |
| ピン 123 | I/O — User I/O pin (bank 4) |
| ピン 124 | I/O — User I/O pin (bank 4) |
| ピン 125 | I/O — User I/O pin (bank 4) |
| ピン 126 | I/O — User I/O pin (bank 4) |
| ピン 127 | I/O — User I/O pin (bank 4) |
| ピン 128 | I/O — User I/O pin (bank 4) |
| ピン 129 | VCCIO — I/O supply voltage |
| ピン 130 | I/O — User I/O pin (bank 4) |
| ピン 131 | I/O — User I/O pin (bank 4) |
| ピン 132 | GND — Ground |
| ピン 133 | I/O — User I/O pin (bank 5) |
| ピン 134 | I/O — User I/O pin (bank 5) |
| ピン 135 | I/O — User I/O pin (bank 5) |
| ピン 136 | I/O — User I/O pin (bank 5) |
| ピン 137 | I/O — User I/O pin (bank 5) |
| ピン 138 | I/O — User I/O pin (bank 5) |
| ピン 139 | I/O — User I/O pin (bank 5) |
| ピン 140 | VCCINT — Core logic supply (5V) |
| ピン 141 | I/O — User I/O pin (bank 5) |
| ピン 142 | I/O — User I/O pin (bank 5) |
| ピン 143 | GND — Ground |
| ピン 144 | I/O — User I/O pin (bank 6) |
| ピン 145 | I/O — User I/O pin (bank 6) |
| ピン 146 | I/O — User I/O pin (bank 6) |
| ピン 147 | I/O — User I/O pin (bank 6) |
| ピン 148 | I/O — User I/O pin (bank 6) |
| ピン 149 | I/O — User I/O pin (bank 6) |
| ピン 150 | I/O — User I/O pin (bank 6) |
| ピン 151 | VCCIO — I/O supply voltage |
| ピン 152 | I/O — User I/O pin (bank 6) |
| ピン 153 | I/O — User I/O pin (bank 6) |
| ピン 154 | GND — Ground |
| ピン 155 | I/O — User I/O pin (bank 7) |
| ピン 156 | I/O — User I/O pin (bank 7) |
| ピン 157 | I/O — User I/O pin (bank 7) |
| ピン 158 | I/O — User I/O pin (bank 7) |
| ピン 159 | I/O — User I/O pin (bank 7) |
| ピン 160 | I/O — User I/O pin (bank 7) |
| ピン 161 | I/O — User I/O pin (bank 7) |
| ピン 162 | VCCINT — Core logic supply (5V) |
| ピン 163 | I/O — User I/O pin (bank 7) |
| ピン 164 | I/O — User I/O pin (bank 7) |
| ピン 165 | GND — Ground |
| ピン 166 | I/O — User I/O pin (bank 8) |
| ピン 167 | I/O — User I/O pin (bank 8) |
| ピン 168 | I/O — User I/O pin (bank 8) |
| ピン 169 | I/O — User I/O pin (bank 8) |
| ピン 170 | I/O — User I/O pin (bank 8) |
| ピン 171 | I/O — User I/O pin (bank 8) |
| ピン 172 | I/O — User I/O pin (bank 8) |
| ピン 173 | VCCIO — I/O supply voltage |
| ピン 174 | I/O — User I/O pin (bank 8) |
| ピン 175 | I/O — User I/O pin (bank 8) |
| ピン 176 | GND — Ground |
| ピン 177 | TDI — JTAG Test Data In |
| ピン 178 | TMS — JTAG Test Mode Select |
| ピン 179 | TCK — JTAG Test Clock |
| ピン 180 | TDO — JTAG Test Data Out |
| ピン 181 | nSTATUS — Configuration status (open drain) |
| ピン 182 | nCONFIG — Configuration control (input, pull-up) |
| ピン 183 | CONF_DONE — Configuration done (open drain) |
| ピン 184 | DCLK — Configuration clock |
| ピン 185 | DATA0 — Configuration data input |
| ピン 186 | nCE — Chip enable (active low) |
| ピン 187 | nWS — Write strobe (active low) |
| ピン 188 | MSEL0 — Configuration mode select 0 |
| ピン 189 | MSEL1 — Configuration mode select 1 |
| ピン 190 | VCCINT — Core logic supply (5V) |
| ピン 191 | I/O — User I/O pin (bank 1) |
| ピン 192 | I/O — User I/O pin (bank 1) |
| ピン 193 | I/O — User I/O pin (bank 1) |
| ピン 194 | I/O — User I/O pin (bank 1) |
| ピン 195 | I/O — User I/O pin (bank 1) |
| ピン 196 | I/O — User I/O pin (bank 1) |
| ピン 197 | I/O — User I/O pin (bank 1) |
| ピン 198 | GND — Ground |
| ピン 199 | I/O — User I/O pin (bank 2) |
| ピン 200 | I/O — User I/O pin (bank 2) |
| ピン 201 | I/O — User I/O pin (bank 2) |
| ピン 202 | I/O — User I/O pin (bank 2) |
| ピン 203 | I/O — User I/O pin (bank 2) |
| ピン 204 | I/O — User I/O pin (bank 2) |
| ピン 205 | I/O — User I/O pin (bank 2) |
| ピン 206 | VCCIO — I/O supply voltage |
| ピン 207 | I/O — User I/O pin (bank 2) |
| ピン 208 | I/O — User I/O pin (bank 2) |
主な用途
EPF8820ARI208-2 の用途: 6 件s: Industrial Glue Logic Replacement, Telecommunications Interface Bridge, ASIC Prototyping Platform, Educational Hardware Design Platform, Legacy Industrial Controller Drop-In, Embedded Control State Machine Hub.
Industrial Glue Logic Replacement
The EPF8820ARI208-2's 672 logic elements and 152 user I/O pins make it ideal for replacing multiple discrete TTL/CMOS glue-logic ICs in industrial controllers. Industrial glue logic typically aggregates 5-15 small logic devices into a single FPGA, simplifying PCB layout and reducing BOM cost. The -2 speed grade is well-matched to control-bus frequencies in the 20-40 MHz range typical of PLC backplanes. Unlike CPLDs, this FPGA's SRAM configuration enables in-field firmware updates via JTAG without removing the board from service.
おすすめ
Telecommunications Interface Bridge
The EPF8820ARI208-2 bridges legacy telecom buses (E1/T1 framers, HDLC controllers, RS-232/RS-485 transceivers) to modern processors in telecom line cards. Its 152 user I/O pins accommodate parallel bus widths of 16-32 bits with spare pins for control signals. The 16 Kbits of embedded SRAM (6 EABs) buffer small packet fragments between interfaces without external memory. Industrial temperature grade (-40C to +85C) ensures operation in central-office and outside-plant cabinets, and the volatile SRAM configuration allows remote firmware upgrades.
おすすめ
ASIC Prototyping Platform
The EPF8820ARI208-2 is used to prototype ASIC designs before tape-out, leveraging its 8,000 usable gates and register-rich architecture. The 4-input LUT plus dedicated register per LE maps efficiently to synthesized RTL, and FastTrack interconnect provides predictable routing delays that closely model ASIC timing. The 208-pin RQFP package exposes 152 user I/Os for connecting to prototype ASIC pads via a daughter-card adapter. In-system reprogrammability via JTAG cuts prototype iteration cycles from weeks to hours, dramatically reducing ASIC development cost.
おすすめ
Educational Hardware Design Platform
Universities and technical colleges use the EPF8820ARI208-2 on FPGA development boards to teach digital design, HDL synthesis, and FPGA architecture concepts. The device's moderate capacity (672 LEs) is large enough to host a complete RISC soft-core plus peripherals, yet small enough to keep tool runtimes manageable on student laptops. The mature MAX+PLUS II toolchain is freely available and well-documented. Industrial temperature grade ensures boards survive lab environments, and the obsolete status makes it affordable for educational budgets.
おすすめ
Legacy Industrial Controller Drop-In
The EPF8820ARI208-2 serves as a drop-in replacement for obsolete FLEX 8000 devices on existing industrial controller PCBs, extending the service life of field-deployed equipment. Its pin-compatible 208-pin RQFP package requires no PCB rework, and the same JTAG programming flow is preserved. Designers can clone the legacy configuration bitstream from a working board and program the new part without modifying firmware. This application is particularly valuable for legacy SCADA, CNC, and process-control systems where full board redesign is cost-prohibitive.
おすすめ
Embedded Control State Machine Hub
The EPF8820ARI208-2 implements complex state machines that coordinate multiple peripherals in embedded systems, replacing discrete PAL/GAL devices with a single reprogrammable part. The 672 LE capacity is well-matched to state machines with 20-50 states and dozens of outputs, and the 16 Kbits of EAB SRAM stores lookup tables for state-transition encoding. JTAG programming allows firmware updates via the same port used for boundary-scan testing, simplifying manufacturing and field-service workflows in industrial automation.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPF8820ARI208-2 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPF8820ARC208-2 | EPF8820ARC208-2N | EPF8820ARI208-1 | EPF8820ARC208-3 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP (RI) | 208-pin RQFP (RC) - same | 208-pin RQFP (RC) - same | 208-pin RQFP (RI) - same | 208-pin RQFP (RC) - same |
| Logic Elements | 672 | 672 | 672 | 672 | 672 |
| Maximum User I/O | 152 | 152 | 152 | 152 | 152 |
| Speed Grade | -2 | -2 (same) | -2 (same) | -1 (slower) | -3 (faster) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Embedded Array Blocks | 6 | 6 | 6 | 6 | 6 |
| Core Voltage (VCCINT) | 5 V | 5 V | 5 V | 5 V | 5 V |
主な差別化要因
- Industrial temperature grade for harsh environments （vs EPF8820ARC208-2)
- Moderate speed grade for power/cost optimization （vs EPF8820ARC208-3)
- Drop-in compatibility with full FLEX 8000 family （vs EPF8820ARI208-1)
設計ノート
Estimated: At 5V VCCINT and 50 MHz internal toggle rate with typical 30% utilization, the EPF8820ARI208-2 draws approximately 200-400 mA from VCCINT. Decouple VCCINT and VCCIO with 0.1 uF ceramic capacitors placed within 5 mm of each supply pin, and add bulk 10-100 uF tantalum or low-ESR ceramic capacitors near the package. The 5V core supply is legacy; modern designs targeting lower power should consider migrating to Cyclone IV or MAX II devices.
The 208-pin RQFP package has a 0.5 mm lead pitch and 28x28 mm body, requiring fine-pitch PCB soldering capability. Maintain at least 4-layer stackup with continuous ground plane beneath the FPGA for controlled impedance and thermal spreading. Route JTAG signals (TDI, TMS, TCK, TDO) with 50 ohm impedance and keep trace lengths matched within 25 mm to satisfy the JTAG specification. Provide test-point access to JTAG pins for in-system programming.
Place the external configuration memory (EPC1, EPC1213, EPC1064, or EPC1441) within 50 mm of the FPGA DCLK and DATA0 pins to minimize configuration signal integrity issues. Keep nCONFIG and nSTATUS traces short and route away from high-frequency switching signals to avoid false triggers during board power-up. Decouple the configuration memory VCC with its own 0.1 uF ceramic capacitor. The FLEX 8000 configuration scheme is sensitive to power-supply ramp time - ensure monotonic VCCINT ramp within 100 ms.
The 5V TTL/CMOS I/O banks support up to 152 user signals; however, simultaneous switching outputs (SSO) can induce ground bounce above 200 MHz toggle rates. Limit SSO to 8-12 outputs per bank switching simultaneously, and add 10-33 ohm series resistors on high-speed outputs to dampen reflections. For applications above 50 MHz, use controlled-impedance traces (50 ohm single-ended) with proper termination at the receiver.
Common pitfalls include: (1) forgetting to connect nCONFIG to VCCINT through a pull-up resistor - leaves the device unconfigured; (2) tying CONF_DONE to ground - prevents configuration completion detection; (3) missing MSEL0/MSEL1 pull-up/down resistors for proper configuration mode selection; (4) omitting JTAG chain integrity resistors on TDO - causes ByteBlaster communication failures; (5) using 3.3V LVCMOS signals directly into 5V VCCIO without level translation - damages I/O cells. Always verify configuration mode settings and JTAG chain with MAX+PLUS II programmer software before design commit.
コンプライアンス情報
RoHS compliance per DigiKey listing for EPF8820ARC208-2 (same family variant). Halogen-free status not explicitly stated in available data; lead-free and RoHS compliant confirmed via distributor listings. Not AEC-Q100 qualified - FPGAs are typically not AEC-Q100 unless explicitly automotive-qualified.
