EPM570GT100C5 - 570 LEs MAX II CPLD, 100-pin TQFP | Intel
部品番号: EPM570GT100C5 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $19.32 | $19.32 |
| 10 | $17.4 | $174.00 |
| 100 | $14.85 | $1,485.00 |
| 500 | $12.62 | $6,310.00 |
| 1,000 | $10.95 | $10,950.00 |
EPM570GT100C5 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses a sum-of-products macrocell fabric to implement glue logic, state machines, bus bridging and interface protocol conversion. In the broader system hierarchy, a CPLD sits alongside the FPGA as a programmable logic category under the broader Programmable Logic umbrella. MAX II devices are designed for low-power, low-cost, non-volatile logic integration, making them ideal companions to microcontrollers, ASSPs and processors that require fast, deterministic boot-time logic and pin-controlled configuration.
Key features of the EPM570GT100C5 include 76 maximum user I/O, 8 Kbits of UFM for storing user data such as firmware parameters or serial numbers, JTAG IEEE 1149.1 boundary-scan and in-system programmability (ISP) via the built-in JTAG interface, MultiVolt I/O for level mixing without external translators, and a commercial operating temperature grade (0 °C to +85 °C). The non-volatile flash configuration enables instant-on behavior with no external boot PROM, unlike SRAM-based FPGAs.
Architecturally, MAX II devices use a logic element (LE) fabric with a continuous routing network and per-I/O programmable pull-ups, slew rate and bus-hold. The 8 Kbit UFM block can be read or written from the logic fabric for parameter storage, and the MultiVolt core allows 1.8 V core operation with mixed-voltage I/O for direct bridging between 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V domains.
Typical applications include power-sequence and reset management, I/O expansion and bus bridging between microcontrollers and peripherals, LED display driving, industrial control logic, glue logic in telecom line cards, and consumer electronics. The instant-on non-volatile fabric makes the device particularly suited to safety-critical or boot-deterministic designs.
When designing, ensure that all I/O banks are powered correctly for the desired interface voltage and that the JTAG chain ordering matches the datasheet. Designers should also budget for the 1.8 V core supply separately from the I/O supply and check that total I/O utilization stays below the 76-pin maximum when accounting for JTAG pins.
This page synthesizes distributor pricing, drop-in MAX II alternatives in the same TQFP-100 footprint and design notes not consolidated in the datasheet PDF.
ドロップイン代替品: EPM570GT100C5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570GT100C5 （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Process Technology, Configuration Memory, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T100C5N
✅ ドロップイン✓ 在庫あり
$10.2 / 個
データシートを見る →EPM570GT100C4N
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM570GT100C3N
✅ ドロップイン✓ 在庫あり
$12.9 / 個
データシートを見る →EPM570GT100C4
✅ ドロップイン✓ 在庫あり
$17.25 / 個
データシートを見る →EPM570GT100C3
✅ ドロップイン✓ 在庫あり
$9.05 / 個
データシートを見る →EPM570GM100C5N
✅ ドロップイン✓ 在庫あり
$10.4 / 個
データシートを見る →EPM570F100C5N
✅ ドロップイン✓ 在庫あり
$5.2 / 個
データシートを見る →EPM570F100A5N
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM570GT100C5 最大定格＆電気的特性
| Family | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LE) | 570 |
| Equivalent Macrocells | 440 |
| User Flash Memory (UFM) | 8 Kbits |
| Maximum User I/O | 76 |
| Propagation Delay (tPD) | 5.4 ns |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltages (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V |
| パッケージ | TQFP-100 (100-pin TQFP, 14x14 mm) |
| 動作温度 | 0 °C to +85 °C (Commercial) |
| Process Technology | 0.30 µm 6-layer-metal flash |
| Programming Interface | JTAG IEEE 1149.1, ISP |
| Configuration Method | Non-volatile flash (instant-on) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
EPM570GT100C5 ピン構成
| ピン 1 | I/O — User I/O - bank 1 |
| ピン 2 | I/O — User I/O - bank 1 |
| ピン 3 | I/O — User I/O - bank 1 |
| ピン 4 | I/O — User I/O - bank 1 |
| ピン 5 | I/O — User I/O - bank 1 |
| ピン 6 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 7 | I/O — User I/O - bank 1 |
| ピン 8 | I/O — User I/O - bank 1 |
| ピン 9 | I/O — User I/O - bank 1 |
| ピン 10 | I/O — User I/O - bank 1 |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O - bank 1 |
| ピン 13 | I/O — User I/O - bank 1 |
| ピン 14 | I/O — User I/O - bank 1 |
| ピン 15 | I/O — User I/O - bank 1 |
| ピン 16 | I/O — User I/O - bank 1 |
| ピン 17 | I/O — User I/O - bank 1 |
| ピン 18 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 19 | I/O — User I/O - bank 1 |
| ピン 20 | I/O — User I/O - bank 1 |
| ピン 21 | I/O — User I/O - bank 1 |
| ピン 22 | I/O — User I/O - bank 1 |
| ピン 23 | I/O — User I/O - bank 1 |
| ピン 24 | GND — Ground |
| ピン 25 | I/O — User I/O - bank 2 |
| ピン 26 | I/O — User I/O - bank 2 |
| ピン 27 | I/O — User I/O - bank 2 |
| ピン 28 | I/O — User I/O - bank 2 |
| ピン 29 | I/O — User I/O - bank 2 |
| ピン 30 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 31 | I/O — User I/O - bank 2 |
| ピン 32 | I/O — User I/O - bank 2 |
| ピン 33 | I/O — User I/O - bank 2 |
| ピン 34 | I/O — User I/O - bank 2 |
| ピン 35 | GND — Ground |
| ピン 36 | I/O — User I/O - bank 2 |
| ピン 37 | I/O — User I/O - bank 2 |
| ピン 38 | I/O — User I/O - bank 2 |
| ピン 39 | I/O — User I/O - bank 2 |
| ピン 40 | I/O — User I/O - bank 2 |
| ピン 41 | I/O — User I/O - bank 2 |
| ピン 42 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 43 | I/O — User I/O - bank 2 |
| ピン 44 | I/O — User I/O - bank 2 |
| ピン 45 | I/O — User I/O - bank 2 |
| ピン 46 | I/O — User I/O - bank 2 |
| ピン 47 | I/O — User I/O - bank 2 |
| ピン 48 | GND — Ground |
| ピン 49 | I/O — User I/O - bank 3 |
| ピン 50 | I/O — User I/O - bank 3 |
| ピン 51 | I/O — User I/O - bank 3 |
| ピン 52 | I/O — User I/O - bank 3 |
| ピン 53 | I/O — User I/O - bank 3 |
| ピン 54 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 55 | I/O — User I/O - bank 3 |
| ピン 56 | I/O — User I/O - bank 3 |
| ピン 57 | I/O — User I/O - bank 3 |
| ピン 58 | I/O — User I/O - bank 3 |
| ピン 59 | GND — Ground |
| ピン 60 | I/O — User I/O - bank 3 |
| ピン 61 | I/O — User I/O - bank 3 |
| ピン 62 | I/O — User I/O - bank 3 |
| ピン 63 | I/O — User I/O - bank 3 |
| ピン 64 | I/O — User I/O - bank 3 |
| ピン 65 | I/O — User I/O - bank 3 |
| ピン 66 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 67 | I/O — User I/O - bank 3 |
| ピン 68 | I/O — User I/O - bank 3 |
| ピン 69 | I/O — User I/O - bank 3 |
| ピン 70 | I/O — User I/O - bank 3 |
| ピン 71 | I/O — User I/O - bank 3 |
| ピン 72 | GND — Ground |
| ピン 73 | I/O — User I/O - bank 4 |
| ピン 74 | I/O — User I/O - bank 4 |
| ピン 75 | I/O — User I/O - bank 4 |
| ピン 76 | I/O — User I/O - bank 4 |
| ピン 77 | I/O — User I/O - bank 4 |
| ピン 78 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 79 | I/O — User I/O - bank 4 |
| ピン 80 | I/O — User I/O - bank 4 |
| ピン 81 | I/O — User I/O - bank 4 |
| ピン 82 | I/O — User I/O - bank 4 |
| ピン 83 | GND — Ground |
| ピン 84 | I/O — User I/O - bank 4 |
| ピン 85 | I/O — User I/O - bank 4 |
| ピン 86 | I/O — User I/O - bank 4 |
| ピン 87 | I/O — User I/O - bank 4 |
| ピン 88 | I/O — User I/O - bank 4 |
| ピン 89 | I/O — User I/O - bank 4 |
| ピン 90 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 91 | I/O — User I/O - bank 4 |
| ピン 92 | I/O — User I/O - bank 4 |
| ピン 93 | I/O — User I/O - bank 4 |
| ピン 94 | I/O — User I/O - bank 4 |
| ピン 95 | I/O — User I/O - bank 4 |
| ピン 96 | GND — Ground |
| ピン 97 | TCK — JTAG test clock |
| ピン 98 | TMS — JTAG test mode select |
| ピン 99 | TDI — JTAG test data in |
| ピン 100 | TDO — JTAG test data out |
主な用途
EPM570GT100C5 の用途: 6 件s: Power-Sequence and Reset Management, I/O Expansion and Bus Bridging, LED Display Driving and Multiplexing, Industrial Glue Logic in Telecom Line Cards, Glue Logic in Consumer Electronics, State Machine and Protocol Conversion.
Power-Sequence and Reset Management
The EPM570GT100C5 is well suited to power-sequence management in multi-rail systems where 76 user I/O and deterministic instant-on timing are needed. Its non-volatile flash configuration means rails come up in the correct order within microseconds of VCCINT crossing threshold, without the configuration latency of an SRAM FPGA. The 8 Kbit UFM can store rail timing parameters (ramp rates, fault thresholds, watchdog windows) that the on-chip logic reads at boot, while the MultiVolt I/O banks allow direct interface to 5 V power-good signals, 3.3 V microcontroller GPIO and 1.8 V SoC rails without external level shifters. Engineers typically use this CPLD to supervise up to 8-10 rails with hot-swap control.
おすすめ
I/O Expansion and Bus Bridging
Use the EPM570GT100C5 to bridge between microcontrollers and peripherals when protocol conversion, GPIO expansion or timing skew correction is required. The 570 LE / 440 macrocell fabric is sufficient to implement UART, SPI, I2C, and parallel-to-serial bridges while staying below the 76 I/O budget. MultiVolt I/O lets the CPLD bridge directly between a 3.3 V MCU and 1.8 V SoC, or between 5 V legacy peripherals and 1.8 V modern controllers, removing external translator ICs. The 5.4 ns tPD in the -5 speed grade is adequate for sub-150 MHz bus rates typical of these bridges, and the JTAG ISP simplifies in-field firmware updates without removing the device.
おすすめ
LED Display Driving and Multiplexing
The EPM570GT100C5 is widely used in LED matrix and seven-segment display driving because its 76 user I/O and 5.4 ns tPD enable high refresh rates without flicker. With its 8 Kbit UFM, display patterns, fonts and animation frames can be stored on-chip and clocked out by the logic fabric, eliminating an external ROM. The MultiVolt I/O banks support both 3.3 V logic-level LED drivers and 5 V common-anode displays from the same device. Commercial 0-85 °C operating range suits indoor signage and consumer display products, and instant-on flash configuration means displays boot deterministically without a controller pre-load.
おすすめ
Industrial Glue Logic in Telecom Line Cards
The EPM570GT100C5 is a typical glue-logic CPLD for telecom line cards, providing backplane interface logic, clock distribution and alarm monitoring around the main processor or ASIC. Its 570 LE and 76 user I/O fit comfortably into line-card glue tasks such as TDM bus steering, MDIO/SPI muxing and watchdog supervision. Commercial extended temperature screening makes it suitable for controlled-environment telecom racks. The instant-on non-volatile configuration ensures the line card comes up in a defined state even before the host CPU boots, which is critical for in-service maintenance and field-replacement scenarios where predictable bring-up behavior is required.
おすすめ
Glue Logic in Consumer Electronics
Consumer electronics designs use the EPM570GT100C5 as cost-effective glue logic to integrate sensors, keypads, audio codecs and display drivers around a main applications processor. The 570 LE capacity fits typical consumer glue tasks, while 76 user I/O supports up to 76 discrete signals without a second CPLD. The instant-on flash configuration removes external boot devices and reduces BOM cost, which is critical in cost-sensitive consumer products. MultiVolt I/O allows direct connection to 5 V audio CODECs and 1.8 V application processors from the same device, simplifying PCB layout and reducing the level-shifter count on the board.
おすすめ
State Machine and Protocol Conversion
Use the EPM570GT100C5 to implement complex state machines for protocol conversion tasks such as SPI-to-UART, I2C-to-parallel, or custom sensor interfaces where an MCU would be over-spec'd. The MAX II fabric's product-term architecture is ideal for sum-of-products state machines and gives fully deterministic timing - critical for industrial control and motor-drive applications. Up to 440 equivalent macrocells support non-trivial state machines with dozens of states, while the 8 Kbit UFM can hold configuration tables or calibration data. With -5 grade tPD of 5.4 ns and 76 I/O, the device comfortably handles multi-master protocol arbitration without external logic.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570GT100C5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T100C5N | EPM570GT100C4N | EPM570GT100C3N | EPM570GT100C4 | EPM570F100C5N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements (LE) | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade (tPD) | -5 (5.4 ns) | -5 (5.4 ns) | -4 (4.5 ns) | -3 (3.6 ns) | -4 (4.5 ns) | -5 (5.4 ns) |
| UFM Size | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Lead-Free (Pb-free) | No (legacy finish) | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) | No | Yes (RoHS) |
| Max User I/O (TQFP-100) | 76 | 76 | 76 | 76 | 76 | 76 |
主な差別化要因
- Faster speed grade available in the same TQFP-100 footprint （vs EPM570GT100C3N)
- RoHS-compliant drop-in replacement without speed compromise （vs EPM570T100C5N)
- F-series package option enables vertical migration （vs EPM570F100C5N)
設計ノート
The EPM570GT100C5 requires a dedicated 1.8 V ±5% VCCINT supply and independent VCCIO1-4 bank supplies (1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V). Decouple each VCCINT pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin and bulk-decouple VCCINT with a 10 µF tantalum. For each VCCIO bank, place a 0.1 µF ceramic plus 4.7 µF bulk within 10 mm. Power sequencing between VCCINT and VCCIO is not strictly required, but the part only initializes when VCCINT crosses 1.8 V; hold the JTAG controller in reset until VCCINT is stable.
Use a 4-layer PCB with a continuous ground plane beneath the EPM570GT100C5 to minimize ground bounce on the parallel I/O bus. Route JTAG signals (TCK, TMS, TDI, TDO) away from high-frequency switching signals and keep them short (<50 mm). Each VCCIO bank can drive up to ~20 mA per pin; distribute high-current loads across multiple I/O banks to balance thermal dissipation. For MultiVolt designs, do not float unused VCCIO banks - tie unused bank supplies to VCCINT (1.8 V) to prevent latch-up during power-up.
MultiVolt I/O outputs slew at rates that can produce ground-bounce on parallel buses wider than ~16 bits. For wide buses, enable the slow-slew-rate option in Quartus II to reduce edge rates by 30-50%. Enable bus-hold on inputs that are not actively driven (such as SPI chip-select lines) to avoid floating CMOS inputs during power transitions. For 5 V-tolerant input tolerance, ensure VCCIO is at 3.3 V or higher; lower VCCIO voltages do not guarantee 5 V input tolerance per the MAX II datasheet.
A common mistake is using the 76 user I/O figure as the number of simultaneously routable I/O; subtract 4 JTAG pins (TCK/TMS/TDI/TDO) and any bank-specific VCCIO/GND pins when budgeting. Do not enable JTAG boundary-scan and JTAG ISP simultaneously unless your TAP controller handles them - configure the JTAG chain order in Quartus II before generating the BSDL file. Finally, do not program the UFM and the logic array in conflicting write cycles; the UFM arbitration must be designed into the fabric to avoid bus contention.
コンプライアンス情報
EPM570GT100C5 is RoHS-compliant per Intel product documentation but uses non-Pb-free ('G' suffix) terminal finish - for new RoHS designs requiring Pb-free finish, use EPM570T100C5N. AEC-Q100 qualification is not applicable; for automotive-grade designs consider EPM570F100A5N or MAX V automotive variants.
