EPM570GT100C5 - 570 LEs MAX II CPLD, 100-pin TQFP | Intel
MPN: EPM570GT100C5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $19.32 | $19.32 |
| 10 | $17.4 | $174.00 |
| 100 | $14.85 | $1,485.00 |
| 500 | $12.62 | $6,310.00 |
| 1,000 | $10.95 | $10,950.00 |
Drop-in alternatives for EPM570GT100C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM570GT100C5 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LE) | 570 |
| Equivalent Macrocells | 440 |
| User Flash Memory (UFM) | 8 Kbits |
| Maximum User I/O | 76 |
| Propagation Delay (tPD) | 5.4 ns |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltages (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V |
| Package | TQFP-100 (100-pin TQFP, 14x14 mm) |
| Operating Temperature | 0 °C to +85 °C (Commercial) |
| Process Technology | 0.30 µm 6-layer-metal flash |
| Programming Interface | JTAG IEEE 1149.1, ISP |
| Configuration Method | Non-volatile flash (instant-on) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
EPM570GT100C5 Pin Configuration
| Pin 1 | I/O — User I/O - bank 1 |
| Pin 2 | I/O — User I/O - bank 1 |
| Pin 3 | I/O — User I/O - bank 1 |
| Pin 4 | I/O — User I/O - bank 1 |
| Pin 5 | I/O — User I/O - bank 1 |
| Pin 6 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 7 | I/O — User I/O - bank 1 |
| Pin 8 | I/O — User I/O - bank 1 |
| Pin 9 | I/O — User I/O - bank 1 |
| Pin 10 | I/O — User I/O - bank 1 |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O - bank 1 |
| Pin 13 | I/O — User I/O - bank 1 |
| Pin 14 | I/O — User I/O - bank 1 |
| Pin 15 | I/O — User I/O - bank 1 |
| Pin 16 | I/O — User I/O - bank 1 |
| Pin 17 | I/O — User I/O - bank 1 |
| Pin 18 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 19 | I/O — User I/O - bank 1 |
| Pin 20 | I/O — User I/O - bank 1 |
| Pin 21 | I/O — User I/O - bank 1 |
| Pin 22 | I/O — User I/O - bank 1 |
| Pin 23 | I/O — User I/O - bank 1 |
| Pin 24 | GND — Ground |
| Pin 25 | I/O — User I/O - bank 2 |
| Pin 26 | I/O — User I/O - bank 2 |
| Pin 27 | I/O — User I/O - bank 2 |
| Pin 28 | I/O — User I/O - bank 2 |
| Pin 29 | I/O — User I/O - bank 2 |
| Pin 30 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 31 | I/O — User I/O - bank 2 |
| Pin 32 | I/O — User I/O - bank 2 |
| Pin 33 | I/O — User I/O - bank 2 |
| Pin 34 | I/O — User I/O - bank 2 |
| Pin 35 | GND — Ground |
| Pin 36 | I/O — User I/O - bank 2 |
| Pin 37 | I/O — User I/O - bank 2 |
| Pin 38 | I/O — User I/O - bank 2 |
| Pin 39 | I/O — User I/O - bank 2 |
| Pin 40 | I/O — User I/O - bank 2 |
| Pin 41 | I/O — User I/O - bank 2 |
| Pin 42 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 43 | I/O — User I/O - bank 2 |
| Pin 44 | I/O — User I/O - bank 2 |
| Pin 45 | I/O — User I/O - bank 2 |
| Pin 46 | I/O — User I/O - bank 2 |
| Pin 47 | I/O — User I/O - bank 2 |
| Pin 48 | GND — Ground |
| Pin 49 | I/O — User I/O - bank 3 |
| Pin 50 | I/O — User I/O - bank 3 |
| Pin 51 | I/O — User I/O - bank 3 |
| Pin 52 | I/O — User I/O - bank 3 |
| Pin 53 | I/O — User I/O - bank 3 |
| Pin 54 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 55 | I/O — User I/O - bank 3 |
| Pin 56 | I/O — User I/O - bank 3 |
| Pin 57 | I/O — User I/O - bank 3 |
| Pin 58 | I/O — User I/O - bank 3 |
| Pin 59 | GND — Ground |
| Pin 60 | I/O — User I/O - bank 3 |
| Pin 61 | I/O — User I/O - bank 3 |
| Pin 62 | I/O — User I/O - bank 3 |
| Pin 63 | I/O — User I/O - bank 3 |
| Pin 64 | I/O — User I/O - bank 3 |
| Pin 65 | I/O — User I/O - bank 3 |
| Pin 66 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 67 | I/O — User I/O - bank 3 |
| Pin 68 | I/O — User I/O - bank 3 |
| Pin 69 | I/O — User I/O - bank 3 |
| Pin 70 | I/O — User I/O - bank 3 |
| Pin 71 | I/O — User I/O - bank 3 |
| Pin 72 | GND — Ground |
| Pin 73 | I/O — User I/O - bank 4 |
| Pin 74 | I/O — User I/O - bank 4 |
| Pin 75 | I/O — User I/O - bank 4 |
| Pin 76 | I/O — User I/O - bank 4 |
| Pin 77 | I/O — User I/O - bank 4 |
| Pin 78 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 79 | I/O — User I/O - bank 4 |
| Pin 80 | I/O — User I/O - bank 4 |
| Pin 81 | I/O — User I/O - bank 4 |
| Pin 82 | I/O — User I/O - bank 4 |
| Pin 83 | GND — Ground |
| Pin 84 | I/O — User I/O - bank 4 |
| Pin 85 | I/O — User I/O - bank 4 |
| Pin 86 | I/O — User I/O - bank 4 |
| Pin 87 | I/O — User I/O - bank 4 |
| Pin 88 | I/O — User I/O - bank 4 |
| Pin 89 | I/O — User I/O - bank 4 |
| Pin 90 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 91 | I/O — User I/O - bank 4 |
| Pin 92 | I/O — User I/O - bank 4 |
| Pin 93 | I/O — User I/O - bank 4 |
| Pin 94 | I/O — User I/O - bank 4 |
| Pin 95 | I/O — User I/O - bank 4 |
| Pin 96 | GND — Ground |
| Pin 97 | TCK — JTAG test clock |
| Pin 98 | TMS — JTAG test mode select |
| Pin 99 | TDI — JTAG test data in |
| Pin 100 | TDO — JTAG test data out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT100C5 is suitable for 6 applications: Power-Sequence and Reset Management, I/O Expansion and Bus Bridging, LED Display Driving and Multiplexing, Industrial Glue Logic in Telecom Line Cards, Glue Logic in Consumer Electronics, State Machine and Protocol Conversion.
Power-Sequence and Reset Management
The EPM570GT100C5 is well suited to power-sequence management in multi-rail systems where 76 user I/O and deterministic instant-on timing are needed. Its non-volatile flash configuration means rails come up in the correct order within microseconds of VCCINT crossing threshold, without the configuration latency of an SRAM FPGA. The 8 Kbit UFM can store rail timing parameters (ramp rates, fault thresholds, watchdog windows) that the on-chip logic reads at boot, while the MultiVolt I/O banks allow direct interface to 5 V power-good signals, 3.3 V microcontroller GPIO and 1.8 V SoC rails without external level shifters. Engineers typically use this CPLD to supervise up to 8-10 rails with hot-swap control.
Recommended
I/O Expansion and Bus Bridging
Use the EPM570GT100C5 to bridge between microcontrollers and peripherals when protocol conversion, GPIO expansion or timing skew correction is required. The 570 LE / 440 macrocell fabric is sufficient to implement UART, SPI, I2C, and parallel-to-serial bridges while staying below the 76 I/O budget. MultiVolt I/O lets the CPLD bridge directly between a 3.3 V MCU and 1.8 V SoC, or between 5 V legacy peripherals and 1.8 V modern controllers, removing external translator ICs. The 5.4 ns tPD in the -5 speed grade is adequate for sub-150 MHz bus rates typical of these bridges, and the JTAG ISP simplifies in-field firmware updates without removing the device.
Recommended
LED Display Driving and Multiplexing
The EPM570GT100C5 is widely used in LED matrix and seven-segment display driving because its 76 user I/O and 5.4 ns tPD enable high refresh rates without flicker. With its 8 Kbit UFM, display patterns, fonts and animation frames can be stored on-chip and clocked out by the logic fabric, eliminating an external ROM. The MultiVolt I/O banks support both 3.3 V logic-level LED drivers and 5 V common-anode displays from the same device. Commercial 0-85 °C operating range suits indoor signage and consumer display products, and instant-on flash configuration means displays boot deterministically without a controller pre-load.
Recommended
Industrial Glue Logic in Telecom Line Cards
The EPM570GT100C5 is a typical glue-logic CPLD for telecom line cards, providing backplane interface logic, clock distribution and alarm monitoring around the main processor or ASIC. Its 570 LE and 76 user I/O fit comfortably into line-card glue tasks such as TDM bus steering, MDIO/SPI muxing and watchdog supervision. Commercial extended temperature screening makes it suitable for controlled-environment telecom racks. The instant-on non-volatile configuration ensures the line card comes up in a defined state even before the host CPU boots, which is critical for in-service maintenance and field-replacement scenarios where predictable bring-up behavior is required.
Recommended
Glue Logic in Consumer Electronics
Consumer electronics designs use the EPM570GT100C5 as cost-effective glue logic to integrate sensors, keypads, audio codecs and display drivers around a main applications processor. The 570 LE capacity fits typical consumer glue tasks, while 76 user I/O supports up to 76 discrete signals without a second CPLD. The instant-on flash configuration removes external boot devices and reduces BOM cost, which is critical in cost-sensitive consumer products. MultiVolt I/O allows direct connection to 5 V audio CODECs and 1.8 V application processors from the same device, simplifying PCB layout and reducing the level-shifter count on the board.
Recommended
State Machine and Protocol Conversion
Use the EPM570GT100C5 to implement complex state machines for protocol conversion tasks such as SPI-to-UART, I2C-to-parallel, or custom sensor interfaces where an MCU would be over-spec'd. The MAX II fabric's product-term architecture is ideal for sum-of-products state machines and gives fully deterministic timing - critical for industrial control and motor-drive applications. Up to 440 equivalent macrocells support non-trivial state machines with dozens of states, while the 8 Kbit UFM can hold configuration tables or calibration data. With -5 grade tPD of 5.4 ns and 76 I/O, the device comfortably handles multi-master protocol arbitration without external logic.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT100C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T100C5N | EPM570GT100C4N | EPM570GT100C3N | EPM570GT100C4 | EPM570F100C5N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements (LE) | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade (tPD) | -5 (5.4 ns) | -5 (5.4 ns) | -4 (4.5 ns) | -3 (3.6 ns) | -4 (4.5 ns) | -5 (5.4 ns) |
| UFM Size | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Lead-Free (Pb-free) | No (legacy finish) | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) | No | Yes (RoHS) |
| Max User I/O (TQFP-100) | 76 | 76 | 76 | 76 | 76 | 76 |
Key Differentiators
- Faster speed grade available in the same TQFP-100 footprint (vs EPM570GT100C3N)
- RoHS-compliant drop-in replacement without speed compromise (vs EPM570T100C5N)
- F-series package option enables vertical migration (vs EPM570F100C5N)
Design Notes
The EPM570GT100C5 requires a dedicated 1.8 V ±5% VCCINT supply and independent VCCIO1-4 bank supplies (1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V). Decouple each VCCINT pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin and bulk-decouple VCCINT with a 10 µF tantalum. For each VCCIO bank, place a 0.1 µF ceramic plus 4.7 µF bulk within 10 mm. Power sequencing between VCCINT and VCCIO is not strictly required, but the part only initializes when VCCINT crosses 1.8 V; hold the JTAG controller in reset until VCCINT is stable.
Use a 4-layer PCB with a continuous ground plane beneath the EPM570GT100C5 to minimize ground bounce on the parallel I/O bus. Route JTAG signals (TCK, TMS, TDI, TDO) away from high-frequency switching signals and keep them short (<50 mm). Each VCCIO bank can drive up to ~20 mA per pin; distribute high-current loads across multiple I/O banks to balance thermal dissipation. For MultiVolt designs, do not float unused VCCIO banks - tie unused bank supplies to VCCINT (1.8 V) to prevent latch-up during power-up.
MultiVolt I/O outputs slew at rates that can produce ground-bounce on parallel buses wider than ~16 bits. For wide buses, enable the slow-slew-rate option in Quartus II to reduce edge rates by 30-50%. Enable bus-hold on inputs that are not actively driven (such as SPI chip-select lines) to avoid floating CMOS inputs during power transitions. For 5 V-tolerant input tolerance, ensure VCCIO is at 3.3 V or higher; lower VCCIO voltages do not guarantee 5 V input tolerance per the MAX II datasheet.
A common mistake is using the 76 user I/O figure as the number of simultaneously routable I/O; subtract 4 JTAG pins (TCK/TMS/TDI/TDO) and any bank-specific VCCIO/GND pins when budgeting. Do not enable JTAG boundary-scan and JTAG ISP simultaneously unless your TAP controller handles them - configure the JTAG chain order in Quartus II before generating the BSDL file. Finally, do not program the UFM and the logic array in conflicting write cycles; the UFM arbitration must be designed into the fabric to avoid bus contention.
Compliance Information
EPM570GT100C5 is RoHS-compliant per Intel product documentation but uses non-Pb-free ('G' suffix) terminal finish - for new RoHS designs requiring Pb-free finish, use EPM570T100C5N. AEC-Q100 qualification is not applicable; for automotive-grade designs consider EPM570F100A5N or MAX V automotive variants.
