EPM9560RC304-20 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera
部品番号: EPM9560RC304-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM9560RC304-20 概要
A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the logic IC hierarchy, the MAX 9000 CPLD sits between simple PLDs and FPGAs: it offers non-volatile EEPROM configuration, deterministic timing, and instant-on operation, making it a programmable logic device (PLD) suited to glue logic, bus interfacing, and state-machine consolidation.
Key features of the EPM9560RC304-20 include 560 macrocells organized in 20 logic array blocks (LABs), 12,000 usable gates, 212 I/O pins, and 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. The device supports configurable I/O operation at 3.3 V or 5 V, enabling mixed-voltage system integration. Its EEPROM configuration retains logic after power-down, eliminating external configuration memory.
The MAX 9000 architecture uses a third-generation Multiple Array MatriX (MAX) structure with fast, predictable interconnect delays. The -20 speed grade delivers 20 ns pin-to-pin tPD and 100 MHz operation, while the 304-pin RQFP package provides 212 I/O for wide bus applications. EEPROM-based logic allows unlimited reprogramming cycles during development.
Typical applications include PCI and ISA bus bridging, telecommunications line-card glue logic, industrial control state machines, and legacy system replacement where instant-on 5 V CPLD logic is required. The 212 I/O count suits wide address/data bus interfacing.
When designing with the EPM9560RC304-20, note that it is a 5.0 V core device with 3.3 V/5 V configurable I/O; verify I/O bank voltage compatibility with connected devices. Because the part is a legacy MAX 9000 device, confirm lifecycle availability before committing to new designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers a single reference for the EPM9560RC304-20 CPLD.
ドロップイン代替品: EPM9560RC304-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC304-20 （同一形状・フットプリント） — 相違点: Package, Speed Grade, Device Type, User I/O Pins, Logic Array Blocks (LABs).
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC304-15
✅ ドロップイン✓ 在庫あり
$9.4 / 個
データシートを見る →EPM9560RC304-10
✅ ドロップイン✓ 在庫あり
$17.6 / 個
データシートを見る →EPM9560RC304-15N
✅ ドロップイン✓ 在庫あり
$19.8 / 個
データシートを見る →EPM9560RC304-15C
✅ ドロップイン✓ 在庫あり
$24.5 / 個
データシートを見る →EPM9560RC304-2
✅ ドロップイン✓ 在庫あり
$55 / 個
データシートを見る →EPM9560RC304-20 最大定格＆電気的特性
| Device Family | MAX 9000 (EPM9560) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| User I/O Lines | 212 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Operating Frequency | 100 MHz |
| Core Supply Voltage | 5.0 V |
| I/O Voltage | 3.3 V or 5 V (configurable) |
| Configuration Technology | EEPROM (in-system programmable) |
| JTAG Interface | IEEE Std. 1149.1 (built-in) |
| パッケージ | 304-pin RQFP |
| 実装タイプ | Surface Mount |
| Logic Array Blocks (LABs) | 20 |
| Speed Grade | -20 |
EPM9560RC304-20 304-pin rqfp ピン配置ガイド
EPM9560RC304-20 (304-pin rqfp パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560RC304-20.
詳細は データシート をご参照ください。
主な用途
EPM9560RC304-20 の用途: 6 件s: PCI and ISA Bus Bridging, Telecommunications Line-Card Glue Logic, Industrial Control State Machines, Legacy System Replacement and Sustaining, Wide Address/Data Bus Interfacing, Prototyping and Development of Custom Logic.
PCI and ISA Bus Bridging
The EPM9560RC304-20 fits PCI and ISA bus bridging because its 212 user I/O and 560 macrocells can implement wide address/data bus decode and handshake logic in a single device. With a 20 ns pin-to-pin propagation delay and 100 MHz operation, it meets the timing budget of legacy 33 MHz PCI and 8 MHz ISA buses with margin. The EEPROM configuration provides instant-on operation, so the bridge is active immediately at power-up without external configuration memory. Designers typically place the CPLD between the host bus and peripheral devices, using 3.3 V or 5 V configurable I/O to match each bus voltage. The trade-off is higher static power than modern low-voltage CPLDs, but the 5.0 V core directly interfaces legacy 5 V buses without level shifters.
おすすめ
Telecommunications Line-Card Glue Logic
The EPM9560RC304-20 suits telecommunications line-card glue logic because its 560 macrocells consolidate multiple discrete logic functions into one EEPROM CPLD, reducing board area and part count. The 212 I/O lines handle wide control and status buses on line cards, while the 20 ns tPD and 100 MHz rating support the timing of TDM and control-plane interfaces. EEPROM non-volatility means the logic is retained through power cycles, critical for always-on telecom equipment. The device's 5.0 V core with 3.3 V/5 V configurable I/O interfaces directly with legacy telecom ASICs and framers. A practical consideration is that the MAX 9000 is a legacy family, so new line-card designs should evaluate modern CPLDs, but for sustaining existing platforms the EPM9560RC304-20 remains a direct replacement.
おすすめ
Industrial Control State Machines
The EPM9560RC304-20 is well suited to industrial control state machines because its 560 macrocells implement complex finite-state machines with deterministic 20 ns timing, eliminating the jitter of software-based control. The 212 I/O lines connect directly to sensors, relays, and motor-driver interfaces, and the 5.0 V core drives industrial 5 V logic without level shifting. EEPROM configuration gives instant-on operation, so the controller is active immediately after power-up, important for safety-interlocked machinery. The 100 MHz maximum frequency provides ample headroom for multi-axis sequencing. Designers should note the device's static power consumption and verify thermal margins in sealed enclosures. For new designs, a modern CPLD may offer lower power, but the EPM9560RC304-20 remains a viable drop-in for existing industrial boards.
おすすめ
Legacy System Replacement and Sustaining
The EPM9560RC304-20 serves legacy system replacement and sustaining programs because it is the original MAX 9000 device used in many 1990s-era boards, allowing drop-in repair without redesign. Its 304-pin RQFP footprint and 560-macrocell architecture match existing sockets, and the 5.0 V core with 3.3 V/5 V configurable I/O preserves original signal levels. EEPROM configuration means the original programming file can be reloaded via the built-in IEEE Std. 1149.1 JTAG interface. The main challenge is availability: as an obsolete part, stock is limited to independent distributors, and counterfeit risk is elevated. Engineers should verify authenticity and consider pin-compatible speed-grade variants such as EPM9560RC304-15 when the exact -20 grade is unavailable.
おすすめ
Wide Address/Data Bus Interfacing
The EPM9560RC304-20 handles wide address/data bus interfacing because its 212 user I/O lines can directly latch, decode, and multiplex buses up to 32 bits wide without external logic. The 560 macrocells implement address comparators, chip-select decoders, and bus-arbitration state machines in one device. With 20 ns tPD and 100 MHz operation, the CPLD meets the setup/hold requirements of legacy microprocessor buses. The 5.0 V core and configurable 3.3 V/5 V I/O allow direct connection to both older 5 V CPUs and newer 3.3 V peripherals. A key design consideration is pin assignment: the 304-pin RQFP provides ample I/O, but careful floorplanning in the MAX+PLUS II toolchain is needed to minimize interconnect delays on wide buses.
おすすめ
Prototyping and Development of Custom Logic
The EPM9560RC304-20 supports prototyping and development of custom logic because its EEPROM configuration allows unlimited reprogramming cycles during the design phase, and the built-in IEEE Std. 1149.1 JTAG interface enables in-system programming without removing the device. With 560 macrocells and 12,000 usable gates, engineers can implement and iterate on glue logic, state machines, and bus interfaces before committing to an ASIC. The 304-pin RQFP package provides 212 I/O for realistic system-level prototyping. The 20 ns tPD and 100 MHz operation give representative timing behavior. A practical note: the MAX 9000 family is programmed with the legacy MAX+PLUS II toolchain, so development environments must support it; for new prototyping, modern CPLDs with current toolchains may be preferable.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC304-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC304-15 | EPM9560RC304-10 | EPM9560RC304-15N | EPM9560RC304-15C |
|---|---|---|---|---|---|
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 20 ns | 15 ns | 10 ns | 15 ns | 15 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| User I/O Lines | 212 | 212 | 212 | 212 | 212 |
| Core Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) |
| Speed Grade | -20 | -15 | -10 | -15N | -15C |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
主な差別化要因
- 212 user I/O in a single 304-pin RQFP （vs EPM9560RC240-20)
- 20 ns deterministic pin-to-pin delay （vs EPM9560RC304-15)
- EEPROM instant-on configuration （vs SRAM-based FPGAs)
- 5.0 V core with 3.3 V/5 V configurable I/O （vs EPM9560RC304-15C)
設計ノート
The EPM9560RC304-20 requires a 5.0 V core supply and supports 3.3 V or 5 V configurable I/O. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus a bulk 10 uF capacitor per power rail. Because the device is a 5.0 V EEPROM CPLD, static current is higher than modern low-voltage CPLDs; estimate total power from the datasheet ICC vs frequency curve for your toggle rate. Estimated: at 100 MHz with typical toggle rates, verify the junction temperature stays within the rated range using the package thermal resistance.
Route the IEEE Std. 1149.1 JTAG signals (TCK, TMS, TDI, TDO) as short, matched traces with a solid ground return, and keep TCK away from high-speed I/O to avoid programming failures. For the 304-pin RQFP, use a ground plane under the device and distribute decoupling capacitors around the package perimeter. Assign wide address/data buses to adjacent I/O pins during floorplanning in the MAX+PLUS II toolchain to minimize interconnect delay and skew.
Do not assume the EPM9560RC304-20 is pin-compatible with the 240-pin EPM9560RC240-20; the packages differ and require different footprints. Confirm the I/O bank voltage (3.3 V vs 5 V) matches connected devices before power-up to avoid over-voltage damage. As an obsolete MAX 9000 device, verify authenticity of purchased stock and confirm the programming file targets the correct speed grade; a -15 or -10 device will meet -20 timing but the reverse is not guaranteed.
コンプライアンス情報
Compliance data not present in the verified web data. The EPM9560RC304-15N variant is a lead-free (N) ordering option; the base EPM9560RC304-20 compliance status must be confirmed with the manufacturer or distributor.
