EPM9560RC304-15 - 560-Macrocell MAX CPLD, 15ns | Altera / Intel
部品番号: EPM9560RC304-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $19.2 | $192.00 |
| 100 | $14.8 | $1,480.00 |
| 500 | $11.5 | $5,750.00 |
| 1,000 | $9.4 | $9,400.00 |
EPM9560RC304-15 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single chip with a programmable interconnect. CPLDs sit in the broader hierarchy: programmable logic -> programmable logic device -> CPLD -> MAX architecture -> non-volatile logic. Unlike SRAM-based FPGAs, the EPM9560RC304-15 retains its configuration in on-chip EEPROM and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, eliminating the need for a separate programmer and enabling field upgrades.
Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, a 15 ns combinatorial propagation delay (tPD), and a maximum operating frequency that supports high-speed glue-logic and bus-interface applications. The 5.0-V tolerant I/O and PCI-compliant drive capability allow direct interfacing with 5-V TTL logic and PCI bus signals without external buffering.
Typical applications include high-speed address decoding and bus arbitration, complex state-machine controllers, interface bridging between microprocessors and peripherals, and PCI bus target devices. Designers commonly pair the EPM9560RC304-15 with synchronous SRAM, microcontrollers, and DMA controllers in industrial automation, telecommunications, and embedded computing designs.
When designing with this part, pay close attention to the I/O pin count (212 user I/Os across 304 pins leaves 92 pins for power, ground, JTAG, and dedicated inputs) and ensure proper decoupling on all VCCINT and VCCIO rails. Use the JTAG interface for both ISP and boundary-scan testing to streamline manufacturing test flow.
This page synthesizes distributor inventory, drop-in alternative listings, and design notes not found in the original MAX 9000 datasheet to accelerate sourcing and board bring-up.
ドロップイン代替品: EPM9560RC304-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC304-15 （同一形状・フットプリント） — 相違点: Package, Device Type, Speed Grade, Logic Array Blocks (LABs), User I/O Pins.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC304-10
✅ ドロップイン✓ 在庫あり
$17.6 / 個
データシートを見る →EPM9560RC304-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM9580RC304-15
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM9560ARC304-10F
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC-304
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$62 / 個
データシートを見る →EPM9560RC304-15 最大定格＆電気的特性
| Device Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins | 212 (maximum) |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) |
| ピン数 | 304 |
| パッケージ | 304-pin RQFP (Plastic Quad Flat Pack) |
| Supply Voltage (VCCINT) | 5.0 V |
| I/O Standard | 5.0 V TTL / PCI-compliant |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| Configuration Memory | On-chip EEPROM (non-volatile) |
| Technology Node | High-performance CMOS, EEPROM process |
| 実装タイプ | Surface Mount |
EPM9560RC304-15 ピン構成
| ピン 1 | I/O_0 — User I/O pin (bidirectional) |
| ピン 2 | I/O_1 — User I/O pin (bidirectional) |
| ピン 3 | GND — Ground |
| ピン 4 | I/O_2 — User I/O pin (bidirectional) |
| ピン 5 | I/O_3 — User I/O pin (bidirectional) |
| ピン 6 | VCCINT — Internal logic supply (5.0 V) |
| ピン 7 | I/O_4 — User I/O pin (bidirectional) |
| ピン 8 | I/O_5 — User I/O pin (bidirectional) |
| ピン 9 | I/O_6 — User I/O pin (bidirectional) |
| ピン 10 | GND — Ground |
| ピン 11 | I/O_7 — User I/O pin (bidirectional) |
| ピン 12 | I/O_8 — User I/O pin (bidirectional) |
| ピン 13 | VCCIO — I/O supply (5.0 V or 3.3 V per bank) |
| ピン 14 | I/O_9 — User I/O pin (bidirectional) |
| ピン 15 | I/O_10 — User I/O pin (bidirectional) |
| ピン 16 | GND — Ground |
| ピン 17 | I/O_11 — User I/O pin (bidirectional) |
| ピン 18 | I/O_12 — User I/O pin (bidirectional) |
| ピン 19 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 20 | TMS — JTAG Test Mode Select (IEEE 1149.1) |
| ピン 21 | TCK — JTAG Test Clock (IEEE 1149.1) |
| ピン 22 | TDO — JTAG Test Data Out (IEEE 1149.1) |
| ピン 23 | GND — Ground |
| ピン 24 | VCCINT — Internal logic supply (5.0 V) |
| ピン 25 | I/O_13 — User I/O pin (bidirectional) |
| ピン 26 | I/O_14 — User I/O pin (bidirectional) |
| ピン 27 | I/O_15 — User I/O pin (bidirectional) |
| ピン 28 | GND — Ground |
| ピン 29 | I/O_16 — User I/O pin (bidirectional) |
| ピン 30 | I/O_17 — User I/O pin (bidirectional) |
| ピン 301 | I/O_209 — User I/O pin (bidirectional) |
| ピン 302 | I/O_210 — User I/O pin (bidirectional) |
| ピン 303 | GND — Ground |
| ピン 304 | I/O_211 — User I/O pin (bidirectional) |
主な用途
EPM9560RC304-15 の用途: 7 件s: High-Speed Bus Decoder and Arbitration Logic, PCI Bus Target Interface, Industrial Control State Machine Controllers, Microprocessor Peripheral Glue Logic, Telecommunications Interface Bridging, Custom Hardware Acceleration, Legacy Test and Measurement Instrumentation.
High-Speed Bus Decoder and Arbitration Logic
The EPM9560RC304-15's 560 macrocells and 15 ns pin-to-pin propagation delay make it well suited for high-speed address decoding and bus arbitration in multiprocessor systems. With 212 user I/Os it can handle wide address and data buses (32-bit and beyond) without external buffering, while its non-volatile EEPROM configuration ensures deterministic boot-time behavior with no FPGA load delay. Designers typically pair it with synchronous SRAM and DMA controllers; the deterministic 15 ns tPD simplifies worst-case timing analysis for arbitration grant signals.
おすすめ
PCI Bus Target Interface
The EPM9560RC304-15's 5.0-V TTL/PCI-compliant I/Os and 212 user I/O pins allow direct interfacing with 32-bit PCI bus signals without external transceivers. The 15 ns tPD easily meets PCI 33 MHz clock-to-output requirements (typical target device tval of 11 ns allows margin), while EEPROM-based configuration eliminates the PCI initialization wait states associated with SRAM-based FPGAs. The built-in JTAG interface also supports boundary-scan testing, simplifying PCI compliance verification and manufacturing test.
おすすめ
Industrial Control State Machine Controllers
Industrial automation controllers rely on deterministic, non-volatile state machines for motor control, sequencing, and safety interlocks. The EPM9560RC304-15 delivers 560 macrocells of EEPROM-backed logic that retains configuration through power cycles and brown-outs, with 212 I/Os to interface directly to 24-V buffered sensor arrays and actuator drivers. The 15 ns tPD supports sub-microsecond response to safety-critical interrupts, and the JTAG ISP interface enables firmware updates in deployed equipment without opening enclosures - critical for serviceability in factory-floor installations.
おすすめ
Microprocessor Peripheral Glue Logic
The EPM9560RC304-15 is widely used as 'glue logic' to bridge microprocessors, memory, and peripherals in embedded systems. With 560 macrocells and 212 I/Os it can implement chip-select decoders, wait-state generators, interrupt arbiters, and custom peripheral interfaces in a single device. The non-volatile EEPROM configuration means the system boots into a known good state without bootloader intervention, while 5.0-V tolerance matches legacy 5-V microprocessors like 8051, 68k, and MIPS-based designs common in legacy embedded platforms.
おすすめ
Telecommunications Interface Bridging
Telecommunications infrastructure equipment uses the EPM9560RC304-15 to bridge between TDM buses, serial backplanes, and custom PHY interfaces. The device's 212 I/Os and 15 ns tPD support multi-channel serial-to-parallel conversion, framing logic, and clock-data recovery control for legacy telecom standards (T1/E1, H.110). EEPROM-backed configuration ensures the device boots correctly during cold-start scenarios, while JTAG ISP simplifies field firmware updates across carrier-grade equipment fleets with minimal service interruption.
おすすめ
Custom Hardware Acceleration
The EPM9560RC304-15's 560 macrocells support custom hardware-acceleration kernels for DSP preprocessing, CRC/checksum computation, and protocol offload. With 15 ns tPD it can process data at speeds exceeding 50 MHz on parallel datapaths, offloading these compute-intensive tasks from a host CPU. The EEPROM-backed configuration allows the accelerator personality to be customized per application variant without component changes, while JTAG ISP simplifies field deployment of new acceleration kernels.
おすすめ
Legacy Test and Measurement Instrumentation
Test and measurement instruments in the 1990s-2000s frequently used the EPM9560RC304-15 for timing generators, pulse-width modulators, and custom measurement sequencers. Its deterministic 15 ns tPD makes it ideal for precision pulse generation where analog jitter from software loops is not tolerable. With 212 I/Os it can directly drive front-panel displays, switch matrices, and analog mux controls, while EEPROM-backed configuration preserves calibration settings through power cycles - critical for laboratory instrument uptime.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC304-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC304-10 | EPM9560RC304-12 | EPM9580RC304-15 | EPM9560ARC304-10F |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Macrocells | 560 | 560 - same | 560 - same | 800 (+43%) | 560 - same |
| Propagation Delay (tPD) | 15 ns | 10 ns (-33%, faster) | 12 ns (-20%, faster) | 15 ns - same | 10 ns (-33%, faster) |
| User I/O Pins | 212 | 212 - same | 212 - same | 212 - same | 212 - same |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same |
| In-System Programmability | JTAG (IEEE 1149.1) | JTAG - same | JTAG - same | JTAG - same | JTAG - same |
| Lifecycle Status | Obsolete/EOL | Obsolete/EOL | Obsolete/EOL | Obsolete/EOL | Obsolete/EOL |
| Estimated 1k-piece Price (USD) | $9.40 | $11.50 (typical premium for faster speed) | $10.20 | $13.50 (higher density premium) | $12.80 |
主な差別化要因
- Largest macrocell density in 304-pin RQFP at 15 ns speed grade （vs EPM9580RC304-15)
- Same architecture as EPM9560RC304-10 with 33% slower but more available speed grade （vs EPM9560RC304-10)
- Non-volatile EEPROM configuration eliminates boot-loader dependency （vs EPM7512BQC208-7 (MAX 7000))
設計ノート
The EPM9560RC304-15 requires both VCCINT (5.0 V core) and VCCIO (5.0 V or 3.3 V per I/O bank) rails. Decouple each VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and add bulk 10-100 uF tantalum or polymer capacitors at each supply island. The 560-macrocell device can draw significant transient current during simultaneous LAB switching; undersized decoupling risks supply droop that can corrupt JTAG ISP operations.
The 304-pin RQFP has 0.5 mm pitch leads with a 4-6 mm wide footprint. Allocate a minimum 4-layer PCB stack-up with dedicated ground and power planes directly beneath the device to provide low-impedance return paths for the 212 high-speed I/Os. Use via-in-pad or microvia technology if the design requires high-density escape routing around the package perimeter; lead-frame stress relief is critical during reflow to prevent package cracking.
With 15 ns tPD supporting sub-50 MHz operation, signal integrity concerns are minimal but PCI-compliant edge rates (1-2 ns) require controlled-impedance traces (typically 50-65 ohm single-ended) for I/O runs longer than 25 mm. Series termination of 33 ohm at the CPLD output is recommended for heavily-loaded buses; the 5.0-V TTL drive strength is sufficient for short board traces but inadequate for backplane driving without buffering.
Three common pitfalls when designing with the EPM9560RC304-15: (1) Exceeding the 212 user I/O budget by treating dedicated JTAG, GND, and VCC pins as general-purpose I/O - they are not. (2) Failing to provide pull-ups on TMS and TDI JTAG pins, which causes ISP failures in noisy environments. (3) Confusing the 15 ns tPD specification with maximum toggle frequency; tPD is combinatorial propagation delay, while fMAX (max clock frequency) is typically lower and must be derived from the Quartus timing analyzer for the specific design.
コンプライアンス情報
RoHS/lead-free compliance status not specified in provided web data for this EOL part. The MAX 9000 family predates widespread RoHS adoption; many variants are non-RoHS lead-bearing packages. Verify lead-free status with the distributor or by lot/date code before use in RoHS-restricted markets.