HI5746KCAZ - 10-Bit 40MSPS Pipelined ADC | Renesas SSOP-28
部品番号: HI5746KCAZ ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.75 | $127.50 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $7.85 | $7,850.00 |
HI5746KCAZ 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete binary codes for digital processing. Within the broader taxonomy, the HI5746 belongs to the pipeline ADC subclass of Nyquist-rate data converters, situated above flash ADCs (faster but lower resolution), successive-approximation-register (SAR) ADCs (lower speed, higher accuracy), and delta-sigma ADCs (oversampling-based high resolution). Pipeline ADCs are ideal for applications requiring 8-14 bits of resolution at conversion rates from 10 MSPS to several hundred MSPS, occupying a key position in the data-converter hierarchy.
Key features of the HI5746KCAZ include 40 MSPS maximum sampling rate, single +5V analog supply operation, an internal sample-and-hold front-end that eliminates the need for external track-and-hold circuitry, and CMOS outputs that drive standard 3.3V/5V digital loads. The differential pipeline topology reduces even-order harmonics and improves common-mode noise rejection, which is critical in communications and imaging front-ends. Internal voltage reference and amplifier circuitry reduce the external BOM while preserving low aperture jitter for accurate sampling of fast signals.
Typical applications include digital video processing, IF sampling in communications receivers, CCD digitizers, medical imaging arrays, ultrasound beamformers, and baseband signal acquisition in software-defined radio. The 40 MSPS throughput comfortably handles component video (up to 27 MSPS for standard definition), instrument data acquisition, and intermediate-frequency subsystems in cable, satellite, and terrestrial set-top boxes.
When designing with this ADC, provide well-decoupled analog and digital supplies, place input series resistors and decoupling capacitors close to the analog input pins, and route the CMOS output bus away from sensitive analog traces. Maintain a stable, low-jitter encode clock and an adequate input anti-alias filter to preserve SFDR performance.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes that complement the manufacturer datasheet, enabling faster component evaluation for video, imaging, and communications designs.
ドロップイン代替品: HI5746KCAZ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: HI5746KCAZ （同一形状・フットプリント） — 相違点: Architecture, Number of Channels, Package, Resolution, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
HI5746KCA
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
HI5746KCB
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$5.3 / 個
データシートを見る →ADC10D020CIVSX/NOPB
✅ ドロップイン✓ 在庫あり
$10.85 / 個
データシートを見る →ADC10738CIWMX/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC124S021CIMMX
✅ ドロップイン✓ 在庫あり
$2.07 / 個
データシートを見る →HI5746KCAZ 最大定格＆電気的特性
| 分解能 | 10 bits |
| Sampling Rate (Max) | 40 MSPS |
| Number of Channels | 1 (single-ended/differential input) |
| Architecture | Pipelined with internal sample-and-hold |
| Analog Supply Voltage | +5 V (typical) |
| Digital Supply Voltage | +5 V (typical, single-supply operation) |
| Input Type | Differential pipelined front-end |
| Output Interface | CMOS-compatible digital outputs |
| Output Code Format | Straight binary / Two's complement |
| Process Technology | CMOS (monolithic) |
| 動作温度範囲 | -40C to +85C |
| パッケージ | 28-pin SSOP |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
HI5746KCAZ ピン構成
| ピン 1 | INA — Differential analog input A (positive) |
| ピン 2 | INB — Differential analog input B (negative) |
| ピン 3 | REF_TOP — Top of internal reference ladder |
| ピン 4 | REF_BOT — Bottom of internal reference ladder |
| ピン 5 | REFT — Internal reference top tap |
| ピン 6 | VREF — Reference voltage bypass pin |
| ピン 7 | GND_A — Analog ground |
| ピン 8 | VD_A — Analog supply (+5V) |
| ピン 9 | CLOCK — Encode clock input |
| ピン 10 | DB0 — Digital output bit 0 (LSB) |
| ピン 11 | DB1 — Digital output bit 1 |
| ピン 12 | DB2 — Digital output bit 2 |
| ピン 13 | DB3 — Digital output bit 3 |
| ピン 14 | GND_D — Digital ground |
| ピン 15 | DB4 — Digital output bit 4 |
| ピン 16 | DB5 — Digital output bit 5 |
| ピン 17 | DB6 — Digital output bit 6 |
| ピン 18 | DB7 — Digital output bit 7 |
| ピン 19 | DB8 — Digital output bit 8 |
| ピン 20 | DB9 — Digital output bit 9 (MSB) |
| ピン 21 | OTR — Out-of-range indicator |
| ピン 22 | OF — Output format / mode select |
| ピン 23 | VD_D — Digital supply (+5V) |
| ピン 24 | DCLK — Data clock output for synchronisation |
| ピン 25 | NC — Not connected (per datasheet) |
| ピン 26 | NC — Not connected (per datasheet) |
| ピン 27 | NC — Not connected (per datasheet) |
| ピン 28 | PAD — Exposed thermal pad tied to GND or NC per package variant |
主な用途
HI5746KCAZ の用途: 6 件s: Digital Video Digitisation, IF Sampling in Communications Receivers, CCD Image Sensor Digitisation, Medical Ultrasound Beamformer, Industrial Instrumentation and Data Acquisition, Set-Top Box and Cable Modem Tuner Stages.
Digital Video Digitisation
The HI5746KCAZ delivers 10-bit resolution at 40 MSPS, comfortably capturing component digital video at standard-definition rates (up to 27 MSPS for CCIR-601) with headroom for oversampled HDTV preprocessing. Compared with 8-bit parts, the extra two bits reduce quantisation banding and chroma crawl in mid-tone gradients, which is critical for broadcast and prosumer video editing equipment. The CMOS outputs directly drive FPGAs and video processors at 3.3V/5V without level translation, simplifying board layout. The pipelined architecture introduces a fixed latency that must be accounted for in frame-synchronised video paths.
おすすめ
IF Sampling in Communications Receivers
With 40 MSPS throughput, the HI5746KCAZ can digitise intermediate-frequency (IF) signals from cable, terrestrial, and satellite set-top box tuners, enabling digital demodulation in software or DSP hardware. The fully differential pipelined front-end rejects common-mode noise injected by tuner IF chains and cable ingress, while 10-bit dynamic range is sufficient for 256/64 QAM constellation decoding. The CMOS outputs easily feed down-stream DSPs and FPGAs at standard logic levels, eliminating level translators. Ensure the encode clock is jitter-free and the input anti-alias filter is matched to the chosen IF frequency.
おすすめ
CCD Image Sensor Digitisation
The HI5746KCAZ pairs naturally with CCD line and area sensors in industrial vision and document imaging applications. At 40 MSPS the converter supports typical 2048-pixel line rates of several kilohertz, with 10-bit resolution preserving dynamic range for grayscale imaging and machine vision inspection. The internal sample-and-hold simplifies the analog front-end by eliminating external track-and-hold circuitry, while the differential input stage rejects common-mode noise from CCD reset transients. Add a correlated-double-sampler front end if very low-light SNR is required.
おすすめ
Medical Ultrasound Beamformer
In ultrasound receiver arrays, the HI5746KCAZ digitises each transducer channel's returning echo at up to 40 MSPS, supporting mid-frequency medical imaging probes (typically 2-10 MHz after down-conversion). The 10-bit dynamic range and pipelined low-latency architecture are well suited to delay-and-sum beamforming across 32-128 element arrays. Differential inputs reject clock and digital switching noise coupled through patient-side analog paths. Designers should carefully manage thermal dissipation when many ADC channels are placed close together on the same board.
おすすめ
Industrial Instrumentation and Data Acquisition
The HI5746KCAZ serves general-purpose 10-bit data acquisition in oscilloscope front-ends, vibration analysers, and automated test equipment where 40 MSPS throughput is sufficient for repetitive or transient signal capture. The CMOS outputs feed standard microprocessors and DSPs without level translation, while internal reference reduces external BOM. Designers should provide adequate input protection, anti-alias filtering, and synchronous sampling for multi-channel acquisition systems; pair with external instrumentation amplifiers for transducer excitation.
おすすめ
Set-Top Box and Cable Modem Tuner Stages
Consumer set-top boxes and cable modem QAM demodulators use the HI5746KCAZ to digitise IF outputs from downstream tuners, enabling digital channel decoding and QAM symbol recovery. At 40 MSPS the converter handles standard digital cable QAM IFs with margin, and 10-bit resolution preserves the SNR floor needed for 256-QAM constellations. The single +5V supply simplifies cost-sensitive consumer designs, and CMOS outputs cut external interface parts. Board-level ESD and surge protection should be added at the tuner/ADC interface.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: HI5746KCAZ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | HI5746KCA | HI5746KCB | ADC10D020CIVSX/NOPB | ADC10738CIWMX/NOPB |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments | Texas Instruments |
| Package | SSOP-28 | SSOP-28 - same | SSOP-28 - same | SSOP-28 - same | SSOP-28 - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10/12 bits configurable |
| Max Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 20 MSPS (dual channel) | 38 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined dual | Pipelined |
| Number of Input Channels | 1 (differential) | 1 (differential) | 1 (differential) | 2 (single-ended) | 1 |
| Supply Voltage | +5 V (analog and digital) | +5 V | +5 V | +3.3 V | +5 V |
| Output Interface | CMOS | CMOS | CMOS | CMOS | CMOS |
| Internal Sample-and-Hold | Yes | Yes | Yes | Yes | Yes |
| Input Type | Differential | Differential | Differential | Single-ended | Single-ended |
主な差別化要因
- 40 MSPS single-channel pipelined throughput in SSOP-28 （vs ADC10D020CIVSX/NOPB)
- Differential pipelined input stage rejecting common-mode noise （vs ADC10738CIWMX/NOPB)
- Single +5V supply operation （vs ADC10D020CIVSX/NOPB)
- Renesas mature-process CMOS 10-bit ADC family （vs ADC124S021CIMMX)
設計ノート
The HI5746KCAZ requires separate analog (+5V) and digital (+5V) supplies. Decouple each pin with a 100 nF ceramic high-frequency bypass cap placed within 5 mm of the supply pin, plus a 10 uF tantalum or polymer bulk cap on each supply. Use a ferrite bead or pi-filter between the analog and digital +5V rails if they are sourced from the same LDO, to prevent digital switching noise from corrupting the analog reference ladder.
Place analog input series resistors, anti-alias filter components, and the differential input capacitors as close to the INA/INB pins as possible. Keep analog and digital grounds separate on the top layer and join them only at the ADC GND pins; use a ground plane under the analog path. Route the CMOS output bus at right angles and away from analog input traces to minimise digital crosstalk into the sensitive input stage.
Drive the HI5746KCAZ encode clock (CLK) from a low-jitter, fast-edge source: a 74FCT or similar gate-buffer within 25 mm of the pin. Use a series damping resistor (10-33 ohm) close to the clock driver if trace length exceeds 25 mm. Excessive clock jitter directly degrades SNR at high analog input frequencies; aim for total jitter below 5 ps RMS for full 40 MSPS performance.
Avoid driving the analog inputs beyond the supply rails or below ground even briefly - the ESD cells are not robust against strong out-of-range transients. Place external clamp diodes if the upstream driver can swing beyond +5V. The on-chip reference is not designed to drive heavy external loads; if multiple ADCs share the reference, buffer it with an external op-amp follower to preserve accuracy.
コンプライアンス情報
RoHS and lead-free per Renesas datasheet. AEC-Q100 not applicable for general-purpose ADC. Halogen-free status not specified in available documentation.