HI5767/2CA - 10-Bit 20MSPS ADC with Internal Reference | Renesas
部品番号: HI5767/2CA ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.49 | $8.49 |
| 10 | $7.62 | $76.20 |
| 100 | $6.18 | $618.00 |
| 500 | $5.2 | $2,600.00 |
| 1,000 | $4.45 | $4,450.00 |
HI5767/2CA 概要
An analog-to-digital converter (ADC) is a data-acquisition component that converts a continuous analog input signal into a discrete digital code suitable for processing by a microprocessor, FPGA, or DSP. Within the broader signal chain, the ADC sits between the analog front end (amplifiers, filters, and multiplexers) and the digital back end, and it is a critical sub-category of data converters (ADCs/DACs). 10-bit pipeline ADCs such as the HI5767 target applications where 60-66 dB of dynamic range is adequate and where low power and high integration matter more than 14- or 16-bit precision.
The headline specifications of the HI5767/2CA include 10-bit resolution, a 20 MHz guaranteed sampling rate (40/60 MSPS variants exist in the same family), CMOS-process construction, an internal 2.5 V voltage reference, and a low-power architecture suitable for portable and industrial applications. The flash-style architecture and parallel word access deliver low-latency conversion suitable for digital-oscilloscope, CCD imaging, and IF-sampling subsystems.
The HI5767/2CA is fabricated in a low-power CMOS process and uses a pipelined multi-stage architecture with on-chip sample-and-hold, enabling wide analog input bandwidth and fast settling time. An integrated reference minimizes external BOM, while parallel CMOS outputs reduce interface complexity in FPGA or ASIC capture paths. The combination of 10-bit resolution and 20 MSPS throughput makes the part well-suited to communication, video, and instrumentation subsystems where cost-effective integration matters more than extreme dynamic range.
Typical applications for the HI5767/2CA include digital video acquisition, set-top box front ends, CCD imaging digitizers, ultrasound beam-formers, digital oscilloscopes, IF-sampling communication receivers, and industrial data-acquisition boards. The wide input bandwidth and integrated reference also make the converter attractive for low-power portable instrumentation and for medical imaging pre-processing pipelines.
When designing with the HI5767/2CA, pay close attention to analog input drive, reference decoupling, and clock jitter. The 10-bit pipeline architecture tolerates modest source impedance, but an input buffer is recommended when driving the ADC from a high-impedance front end. The integrated reference requires 0.1 uF decoupling on each reference pin as shown in the manufacturer datasheet typical-application circuit.
This page synthesizes distributor pricing, drop-in same-family and cross-brand ADC alternatives, and practical design notes for the HI5767/2CA beyond what is found in the manufacturer datasheet alone.
ドロップイン代替品: HI5767/2CA — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: HI5767/2CA （同一形状・フットプリント） — 相違点: Architecture, Package, Resolution, RoHS Status, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
HI5714/7CB-T
✅ ドロップイン✓ 在庫あり
$9.2 / 個
データシートを見る →HI5767/4CA
✅ ドロップイン✓ 在庫あり
$10.2 / 個
データシートを見る →HI5767/6CA
✅ ドロップイン✓ 在庫あり
$3.4 / 個
データシートを見る →HI5766KCAZ
✅ ドロップイン✓ 在庫あり
$5.6 / 個
データシートを見る →ADS7825UG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
HI5767/2CA 最大定格＆電気的特性
| 分解能 | 10 bit |
| サンプリングレート | 20 MSPS (40/60 MSPS in family variants) |
| Architecture | CMOS Pipelined |
| Number of Channels | 1 |
| Conversion Method | Flash / Pipelined |
| Data Interface | Parallel CMOS, Word Access |
| Internal Voltage Reference | Yes (integrated) |
| パッケージ | 28-pin QSOP (PDSO28) |
| 実装タイプ | Surface Mount |
| Manufacturer | Renesas (formerly Intersil, formerly Harris) |
| RoHS ステータス | unknown |
HI5767/2CA 28-pin qsop (pdso28) ピン配置ガイド
HI5767/2CA (28-pin qsop (pdso28) パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: HI5767/2CA.
詳細は データシート をご参照ください。
主な用途
HI5767/2CA の用途: 7 件s: Digital Video Digitizing, Set-Top Box Tuner Digitizer, CCD Imaging Digitizer, Digital Oscilloscope Front End, IF-Sampling Communication Receiver, Industrial Data Acquisition Card, Medical Imaging Pre-Processing.
Digital Video Digitizing
The HI5767/2CA's 10-bit resolution at 20 MSPS suits 4FSC digital video, progressive-scan SDTV and consumer recorder front ends. The integrated 2.5 V reference removes the external reference IC from the analog front end, simplifying the PCB while keeping the signal chain stable across long temperature excursions. Placed after an anti-alias filter and a low-noise gain stage, the converter outputs parallel CMOS data for an FPGA or ASIC video processor. The 20 MHz Nyquist comfortably handles composite and component SDTV, while the wide analog input bandwidth suppresses sample-rate-dependent gain droop.
おすすめ
Set-Top Box Tuner Digitizer
The HI5767/2CA delivers 20 MSPS into a QSOP-28 footprint suitable for IF-sampling in mid-tier set-top boxes and hybrid analog/digital tuner designs. The integrated voltage reference simplifies the BOM for cost-sensitive consumer products, while the parallel CMOS output interfaces directly to a low-cost FPGA or demodulator with no serializer overhead. The 10-bit dynamic range (~60 dB) is adequate for broadcast IF demodulation where adjacent-channel suppression is handled in the digital baseband. Drops in as a 20 MSPS option with higher-speed 40/60 MSPS siblings in the same footprint for premium tuner families.
おすすめ
CCD Imaging Digitizer
Camera, scanner, and CCD imaging front ends rely on 10-12 bit ADCs with low-noise integrated references to digitize correlated-double-sampled pixel streams. The HI5767/2CA provides 20 MSPS sample rate with an internal 2.5 V reference, eliminating the noise and drift typically introduced by an external reference IC. Its low-latency parallel CMOS output suits line-scan and area-array imaging pipelines at VGA/SVGA resolutions. Placed after a CCD-output buffer, the ADC feeds a camera-link or USB-Vision digital capture block.
おすすめ
Digital Oscilloscope Front End
Low-cost 10-20 MSPS ADC inputs are commonly used in mid-tier digital oscilloscopes, data loggers, and vibration analyzers where 60 dB of dynamic range is sufficient. The HI5767/2CA's integrated reference and parallel CMOS output keep the front-end BOM compact for sub-$1k bench instruments. Its 28-pin QSOP package fits behind a custom FPGA pin arrangement without ballooning PCB real estate. The wide analog input bandwidth supports 10-20 MHz oscilloscope front ends and helps capture fast transient edges.
おすすめ
IF-Sampling Communication Receiver
Software-defined radio and baseband IF-sampling architectures in 2.4 GHz WLAN, point-to-point microwave, and licensed-band narrowband radios use 10-bit ADCs at 20 MSPS to digitize 1-7 MHz IF signals. The HI5767/2CA's wide analog input bandwidth and low latency improve receiver dynamic range while the internal reference maintains gain stability over temperature. The parallel CMOS output connects directly to a DSP or FPGA for digital down-conversion and demodulation.
おすすめ
Industrial Data Acquisition Card
Multi-channel industrial data-acquisition (DAQ) boards use 10-12 bit ADCs for transducer measurement, vibration analysis, and machine-condition monitoring. The HI5767/2CA's 20 MSPS throughput and integrated reference simplify multi-card synchronization and minimize drift across rack-mount chassis. The QSOP-28 footprint accommodates high-density layouts where multiple ADC channels sit side-by-side with dedicated FPGA capture blocks. Supports low-power bench/DIN-rail DAQ designs in factory-automation systems.
おすすめ
Medical Imaging Pre-Processing
Portable medical imaging applications such as handheld ultrasound, low-cost optical coherence tomography (OCT), and biopsy-image digitizers use 10-12 bit ADCs at 20 MSPS to balance dynamic range with low power. The HI5767/2CA's integrated reference reduces analog front-end complexity and supports compact, lightweight designs critical for handheld medical instruments. The QSOP-28 footprint allows for a tight signal-chain layout that minimizes EMI pickup adjacent to the transducer array.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: HI5767/2CA — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | HI5714/7CB-T | HI5767/4CA | HI5767/6CA | HI5766KCAZ | ADS7825UG4 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics (formerly Intersil, Harris) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 28-pin QSOP (PDSO28) | 28-pin QSOP - same | 28-pin QSOP - same | 28-pin QSOP - same | 28-pin QSOP - same | 28-pin QSOP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit |
| Internal Reference | Yes (integrated 2.5 V) | Yes | Yes | Yes | Yes | External |
| Data Interface | Parallel CMOS, Word Access | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Serial |
| Lifecycle Status | Obsolete | Active (some variants) | Obsolete (same die) | Obsolete (same die) | Obsolete | Active |
| Architecture | CMOS Pipelined | CMOS | CMOS Pipelined | CMOS Pipelined | CMOS | SAR |
主な差別化要因
- Integrated 2.5 V internal voltage reference （vs ADS7825UG4)
- Higher sampling rate for video and IF （vs ADS7825UG4)
- Parallel word-access CMOS interface （vs ADS7825UG4)
設計ノート
Place the 0.1 uF reference-decoupling capacitors as close as possible to the VREF and VREFN pins of the HI5767/2CA. The internal voltage reference is sensitive to switching noise coupled through the analog ground plane. Keep digital output traces routed away from the reference and analog input pins to avoid code-correlated noise. A solid ground plane with a star connection at the ADC's GND pin is recommended.
The 28-pin QSOP package has a 0.025-inch lead pitch. Use a 4-layer PCB with a dedicated analog ground plane and a digital ground plane joined at a single point below the ADC's GND pin. Trace the analog input on the top layer surrounded by analog ground fill, and route parallel CMOS outputs on inner layers to control impedance. Keep the analog input trace length below 1 inch to minimize aperture errors.
A high-quality, low-jitter clock is critical for the HI5767/2CA. Estimated: 10-bit resolution at 20 MSPS tolerates up to ~3 ps rms clock jitter before SNR degradation becomes measurable. Source the clock from a dedicated oscillator or a low-jitter clock synthesizer rather than routing an FPGA LVCMOS output with shared power. If the clock must be shared, add a clock buffer to minimize duty-cycle distortion.
Do not operate the HI5767/2CA with analog inputs that exceed the supply rails. The CMOS input structure will undergo latch-up if the input sits outside the analog supply by more than 0.3 V. The integrated 2.5 V reference does not tolerate external loading; do not connect external resistive divider networks to VREF. If multiple voltage rails exist, power up the analog supply first and power down the digital supply last.
コンプライアンス情報
Compliance data not present in the Verified Web Data; parts manufactured before 2006 may predate RoHS disclosure. HI5767/2CA datasheets do not list RoHS or REACH status. Contact Renesas or authorized distributors for an updated compliance certificate.
