ISLA212P20IRZ - 12-Bit 200MSPS SAR ADC, 72-QFN | Renesas
部品番号: ISLA212P20IRZ ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.72 | $38.72 |
| 10 | $34.85 | $348.50 |
| 100 | $28.4 | $2,840.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $19.55 | $19,550.00 |
ISLA212P20IRZ 概要
What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a sampling converter that uses a binary-search algorithm against a precision DAC to resolve the input voltage one bit per clock cycle. SAR ADCs sit in the data-converter hierarchy as ADC -> Nyquist/oversampling ADC -> mixed-signal IC -> semiconductor. They offer excellent linearity, deterministic latency, and low power compared to flash or pipeline converters at moderate sample rates, making them well-suited to instrumentation, communications baseband, and wideband test equipment.
Key headline specifications of the ISLA212P20IRZ include 12-bit resolution, 200 MSPS sampling rate, LVDS/CMOS-selectable digital outputs, SPI configuration port, and -40 °C to +85 °C industrial operating range. The device supports both single-data-rate (full-width SDR) and double-data-rate (half-width DDR) output modes, giving system designers flexibility for FPGA, ASIC, or DSP capture. A 72-contact QFN package with an exposed paddle supplies a low thermal-resistance path for high-clock full-rate operation.
Architecturally, the part uses FemtoCharge™ switched-capacitor input sampling and an internal high-precision reference, with optional external reference support. Its pipeline-style latency is deterministic and pipelined-friendly, simplifying FPGA capture at multi-hundred-megasample rates. Gain, offset, and output timing are adjustable through the SPI port, supporting per-channel calibration in multi-board systems.
Typical applications for the ISLA212P20IRZ include wideband test and measurement instruments, radar IF/baseband digitizers, communications receiver baseband I/Q capture, medical imaging front-ends, and high-channel-count data-acquisition systems. The combination of 12-bit resolution, 200 MSPS throughput, and low power suits portable and ruggedized platforms where thermal density must be controlled.
Designers should provide adequate ground and decoupling on the analog and digital rails, follow the exposed-paddle soldering recommendations (see manufacturer application layout), and verify SPI configuration timing during bring-up. When migrating between family members, no PCB rework is required.
This page synthesizes distributor pricing, validated drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet header alone.
ドロップイン代替品: ISLA212P20IRZ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ISLA212P20IRZ （同一形状・フットプリント） — 相違点: Architecture, Input Type, Operating Temperature, Data Interface, Number of Input Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ISLA212P13IRZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ISLA212P25IRZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ISLA212P20
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ISL26712IHZ-T
✅ ドロップイン✓ 在庫あり
$3.96 / 個
データシートを見る →HI5812JIBZ-T
✅ ドロップイン✓ 在庫あり
$3.95 / 個
データシートを見る →ISLA212P20IRZ 最大定格＆電気的特性
| Number of Bits | 12 |
| Sampling Rate (Per Second) | 200 MSPS |
| Number of Inputs | 1 |
| Architecture | SAR |
| Data Interface | Serial, SPI (configuration); LVDS or CMOS (data) |
| パッケージ / ケース | 72-VFQFN Exposed Pad, 10 mm x 10 mm |
| 実装タイプ | Surface Mount |
| 動作温度 | -40 °C to +85 °C |
| Output Format | LVDS or CMOS, SDR or DDR |
| Configuration Port | SPI |
| Input Type | Single-ended / differential (femtoCharge™ switched-cap) |
| RoHS ステータス | Compliant |
| Process Technology | Standard CMOS with proprietary FemtoCharge™ sampling |
| Packaging | Tray |
ISLA212P20IRZ ピン構成
| ピン 1 | AVDD — Analog supply voltage |
| ピン 2 | AVDD — Analog supply voltage |
| ピン 3 | AGND — Analog ground |
| ピン 4 | AIN+ — Differential analog input (positive) |
| ピン 5 | AIN- — Differential analog input (negative) |
| ピン 6 | AGND — Analog ground |
| ピン 7 | REF — Reference voltage decoupling |
| ピン 8 | REFGND — Reference ground |
| ピン 9 | CLK+ — Differential clock input (positive) |
| ピン 10 | CLK- — Differential clock input (negative) |
| ピン 11 | AGND — Analog ground |
| ピン 12 | AVDD — Analog supply voltage |
| ピン 13 | AVDD — Analog supply voltage |
| ピン 14 | DRVDD — Digital driver supply |
| ピン 15 | DRVSS — Digital driver ground |
| ピン 16 | OUT1+ — LVDS/CMOS data output bit 1 (positive) |
| ピン 17 | OUT1- — LVDS data output bit 1 (negative) |
| ピン 18 | OUT2+ — LVDS/CMOS data output bit 2 (positive) |
| ピン 19 | OUT2- — LVDS data output bit 2 (negative) |
| ピン 20 | OUT3+ — LVDS/CMOS data output bit 3 (positive) |
| ピン 21 | OUT3- — LVDS data output bit 3 (negative) |
| ピン 22 | OUT4+ — LVDS/CMOS data output bit 4 (positive) |
| ピン 23 | OUT4- — LVDS data output bit 4 (negative) |
| ピン 24 | DRVDD — Digital driver supply |
| ピン 25 | OUT5+ — LVDS/CMOS data output bit 5 (positive) |
| ピン 26 | OUT5- — LVDS data output bit 5 (negative) |
| ピン 27 | OUT6+ — LVDS/CMOS data output bit 6 (positive) |
| ピン 28 | OUT6- — LVDS data output bit 6 (negative) |
| ピン 29 | OUT7+ — LVDS/CMOS data output bit 7 (positive) |
| ピン 30 | OUT7- — LVDS data output bit 7 (negative) |
| ピン 31 | OUT8+ — LVDS/CMOS data output bit 8 (positive) |
| ピン 32 | OUT8- — LVDS data output bit 8 (negative) |
| ピン 33 | DRVDD — Digital driver supply |
| ピン 34 | OUT9+ — LVDS/CMOS data output bit 9 (positive) |
| ピン 35 | OUT9- — LVDS data output bit 9 (negative) |
| ピン 36 | OUT10+ — LVDS/CMOS data output bit 10 (positive) |
| ピン 37 | OUT10- — LVDS data output bit 10 (negative) |
| ピン 38 | OUT11+ — LVDS/CMOS data output bit 11 (positive) |
| ピン 39 | OUT11- — LVDS data output bit 11 (negative) |
| ピン 40 | DCLK+ — Data clock output (positive) |
| ピン 41 | DCLK- — Data clock output (negative) |
| ピン 42 | DRVSS — Digital driver ground |
| ピン 43 | DVDD — Digital core supply |
| ピン 44 | DVSS — Digital core ground |
| ピン 45 | SPI_CLK — SPI configuration clock |
| ピン 46 | SPI_SDIO — SPI serial data input/output |
| ピン 47 | SPI_CSB — SPI chip select (active low) |
| ピン 48 | SPI_SDO — SPI serial data output |
| ピン 49 | RESETN — Reset (active low) |
| ピン 50 | PD — Power-down (active high) |
| ピン 51 | MODE — LVDS/CMOS output mode select |
| ピン 52 | FMT — Output format select (SDR/DDR) |
| ピン 53 | DVDD — Digital core supply |
| ピン 54 | DVSS — Digital core ground |
| ピン 55 | NC — Not connected |
| ピン 56 | NC — Not connected |
| ピン 57 | AVDD — Analog supply voltage |
| ピン 58 | AGND — Analog ground |
| ピン 59 | NC — Not connected |
| ピン 60 | NC — Not connected |
| ピン 61 | NC — Not connected |
| ピン 62 | NC — Not connected |
| ピン 63 | AVDD — Analog supply voltage |
| ピン 64 | AGND — Analog ground |
| ピン 65 | NC — Not connected |
| ピン 66 | NC — Not connected |
| ピン 67 | NC — Not connected |
| ピン 68 | NC — Not connected |
| ピン 69 | AVDD — Analog supply voltage |
| ピン 70 | AVDD — Analog supply voltage |
| ピン 71 | AVSS — Analog substrate ground |
| ピン 72 | AVSS — Analog substrate ground |
主な用途
ISLA212P20IRZ の用途: 6 件s: Wideband Test & Measurement Instrumentation, Radar IF / Baseband Digitizer, Communications Receiver Baseband I/Q Capture, Medical Imaging Front-End, Multi-Channel Data Acquisition Systems, Software Defined Radio (SDR) Baseband.
Wideband Test & Measurement Instrumentation
The ISLA212P20IRZ is well suited to wideband digitizers and oscilloscope front-ends where 12-bit dynamic range at 200 MSPS captures fast transients with deterministic SAR latency. Placed between an anti-alias filter and an FPGA, it delivers 200 million samples per second with low aperture uncertainty, and the LVDS DDR output mode eases multi-board synchronization. Compared to a pipelined ADC at similar speed, the SAR topology provides reproducible single-cycle latency, simplifying trigger and time-base firmware. Renesas' FemtoCharge™ input stage supports differential drive from op-amp drivers like the ISL28133.
おすすめ
Radar IF / Baseband Digitizer
For radar IF and baseband digitizers, the ISLA212P20IRZ's 200 MSPS throughput and 12-bit resolution meet the Nyquist criterion for intermediate frequencies in the tens of MHz while preserving phase accuracy for coherent processing. The deterministic SAR latency aligns with radar PRI/PAP timing, which is important for phased-array systems where sample timing must be reproducible across channels. The 72-QFN exposed-paddle package supports continuous full-rate operation without additional heatsinking. For higher IF frequencies, an upgrade to the ISLA212P25IRZ (250 MSPS) is a pin-compatible drop-in.
おすすめ
Communications Receiver Baseband I/Q Capture
In communications baseband receivers, the ISLA212P20IRZ captures I/Q baseband signals at sufficient sample rate for 40 MHz-class LTE and DVB demodulators. The 12-bit resolution and LVDS DDR output mode pair naturally with FPGAs performing matched filtering and demodulation. SAR latency deterministic across resets simplifies AGC loop tuning with a digital feedback path. The pin-compatible ISLA212P25IRZ supports wider bandwidth carrier aggregation in the same footprint when needed.
おすすめ
Medical Imaging Front-End
Medical imaging front-ends including ultrasound and CT baseband digitizers leverage the ISLA212P20IRZ's 200 MSPS sample rate and 12-bit resolution to capture low-amplitude return signals with adequate dynamic range. The SAR architecture provides low-latency single-cycle conversion, which is beneficial for time-gain compensation (TGC) loops. The exposed-paddle QFN package supports the thermal profile of continuous full-rate acquisition. Pairing with low-noise front-end amplifiers like the ISL28633 yields full-channel performance.
おすすめ
Multi-Channel Data Acquisition Systems
Multi-channel data acquisition systems using the ISLA212P20IRZ benefit from synchronized LVDS DDR outputs that ease FPGA pin budgeting when several ADCs are sampled in parallel. The 72-QFN exposed-paddle package supports dense board layouts while dissipating the moderate continuous power of 200 MSPS operation. Channel-to-channel gain and offset calibration is handled through the shared SPI port, enabling per-channel trim in factory acceptance testing. Pin-compatible family members (ISLA212P13IRZ, ISLA212P25IRZ) cover a range of channel-sample-rate tradeoffs.
おすすめ
Software Defined Radio (SDR) Baseband
In software-defined radio baseband designs, the ISLA212P20IRZ captures I/Q streams from analog front-ends at 200 MSPS, giving FPGAs sufficient oversampling for digital down-conversion and decimation. The 12-bit dynamic range supports wideband demodulation of LTE, Wi-Fi, and proprietary waveforms. The exposed-paddle 72-QFN package keeps board density high, important for compact SDR modules. The pin-compatible ISLA212P25IRZ allows the same PCB to be deployed at higher bandwidth when needed.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ISLA212P20IRZ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ISLA212P13IRZ | ISLA212P25IRZ | ISL26712IHZ-T | HI5812JIBZ-T |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 72-QFN (10x10) | 72-QFN (10x10) - same | 72-QFN (10x10) - same | 72-QFN (10x10) - same | 72-QFN (10x10) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Architecture | SAR | SAR | SAR | Sigma-Delta | SAR |
| Data Interface | LVDS/CMOS, SPI config | LVDS/CMOS, SPI config | LVDS/CMOS, SPI config | Serial | Parallel |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Technology | FemtoCharge™ CMOS | FemtoCharge™ CMOS | FemtoCharge™ CMOS | Sigma-delta CMOS | CMOS SAR |
主な差別化要因
- Pin-compatible family spans 130/200/250 MSPS in one footprint （vs ISLA212P13IRZ and ISLA212P25IRZ)
- FemtoCharge™ switched-cap input technology （vs ISL26712IHZ-T (sigma-delta))
- LVDS/CMOS selectable output with SDR/DDR modes （vs HI5812JIBZ-T (parallel CMOS only))
設計ノート
The 72-QFN package with exposed thermal paddle must be soldered to a thermal land on the PCB to maintain junction temperature at full 200 MSPS operation. Use a 0.6 mm pitch QFN land pattern with 9 thermal vias in the paddle (0.3 mm drill, 0.65 mm pitch) under the exposed pad. Decouple each analog and digital supply pin with a 100 nF X7R ceramic placed within 2 mm of the pin, with a 10 uF bulk cap nearby. Separate analog and digital ground planes, stitching under the paddle only with single-point vias.
Do not route SPI configuration lines near the LVDS data outputs or near the analog input traces - SPI is a 10 MHz-class signal and can inject common-mode noise into sensitive ADC front-ends. Keep SPI bus length under 50 mm and place a 33 ohm series resistor at the SDIO pin to dampen reflections. Apply SPI resets on power-up before enabling the analog front-end. Failing to reset causes unpredictable calibration states on the first samples.
Differential analog input traces (AIN+, AIN-) must be length-matched within 0.5 mm and routed as a 100 ohm differential pair on the top layer over a continuous ground plane. Avoid routing these traces across digital or clock splits on the PCB. The differential clock (CLK+, CLK-) is similarly length-matched. Source-series termination (33-50 ohm) at the ADC clock pins reduces reflection-induced jitter. Maintain 5x trace spacing from adjacent LVDS pairs to limit crosstalk.
コンプライアンス情報
RoHS compliance confirmed across DigiKey, Mouser, LCSC catalog pages; -IRZ suffix denotes industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified - refer to the ISLA212P20IRZ-Q1 variant if automotive qualification is required.
